Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems

Abstract

The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI hierarchical array architecture for balanced (2 n -1, 2 n , 2 n +1) and unbalanced (2 k -1, 2 k , 2 k +1) word-length moduli are proposed which is capable of handling signed input numbers. Balanced 2 n -1 SRM is used as a reference to design an unbalanced 2 k -1 and 2 k +1. The synthesized results show that the proposed 2 n -1 SRM architecture achieves 17% of the area, 26% of speed and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the literature. The proposed 2 n +1 SRM architecture achieves 23% of the area, 20% of speed and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel hierarchical approach adopted for the design which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2 n -1, 2 n , 2 n +1} special moduli set based RNS processor and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA).