IEEE Circuits and Systems Magazine最新文献

{"title":"IEEE Access","authors":"","doi":"10.1109/mcas.2024.3392990","DOIUrl":"https://doi.org/10.1109/mcas.2024.3392990","url":null,"abstract":"","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"20 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141064198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Circuits and Systems Magazine Publication Information","authors":"","doi":"10.1109/mcas.2024.3373289","DOIUrl":"https://doi.org/10.1109/mcas.2024.3373289","url":null,"abstract":"","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"54 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141058905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PCI-Express: Evolution of a Ubiquitous Load-Store Interconnect Over Two Decades and the Path Forward for the Next Two Decades","authors":"Debendra Das Sharma","doi":"10.1109/mcas.2024.3373556","DOIUrl":"https://doi.org/10.1109/mcas.2024.3373556","url":null,"abstract":"The Peripheral Component Interconnect Express (PCI-Express or PCle) architecture has been the ubiquitous backbone interconnect in the evolving computing landscape for more than two decades. This paper delves into the multiple innovations driving the backward-compatible evolution of PCle for seven generations, doubling bandwidth every generation, while delivering power-efficient and cost-effective performance. Compute Express Link (CXL) overlays coherency and memory protocols on top of PCle for heterogeneous computing, addressing the memory wall, resource pooling and sharing across servers, and distributed computing using load-store based messaging. The die-todie industry-standard, Universal Chiplet Interconnect Express <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$^{TM}$ </tex-math></inline-formula> (UCle), offers orders of magnitude improvement in bandwidth density, power efficiency, and latency for PCle and CXL protocols on-package and pod-level connectivity with co-packaged optics. We foresee PCle will continue to evolve over the next few decades to serve future computing needs. It will do so by embracing alternate media while backward-compatible frequency scaling with copper will continue and protocol enhancements will enable non-tree fabric topologies.","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"56 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141064165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Impact of Circuits and Systems on the Etna Valley Site [CAS Regional Report]","authors":"Luigi Fortuna, Arturo Buscarino","doi":"10.1109/mcas.2024.3370495","DOIUrl":"https://doi.org/10.1109/mcas.2024.3370495","url":null,"abstract":"The impact of Circuits and Systems, and in particular Cellular Nonlinear Networks (CNNs), on the scientific community of the Etna Valley is briefly remarked. These topics have been the key-point activities that established a permanent link among various researchers, increasing the scientific and industrial relevance of the Etna Valley site in many Circuits and Systems related research areas.","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"66 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141058910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cryogenic CMOS Design for Qubit Control: Present Status, Challenges, and Future Directions [Feature]","authors":"Sudipto Chakraborty, Rajiv V. Joshi","doi":"10.1109/mcas.2024.3383808","DOIUrl":"https://doi.org/10.1109/mcas.2024.3383808","url":null,"abstract":"This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems.","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"25 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141058916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial: Special Issue for the 75th Anniversary of the IEEE Circuits and Systems Society [Editorial]","authors":"Keshab K. Parhi, Hai Li, Krishnan Kailas, Harish Krishnaswamy, Massimo Alioto, Maciej Ogorzalek","doi":"10.1109/mcas.2024.3384522","DOIUrl":"https://doi.org/10.1109/mcas.2024.3384522","url":null,"abstract":"IEEE Circuits and Systems (CAS) Society (CASS) celebrates the 75th Anniversary of the Society in 2024. This is a major celebration for CASS after the Golden Jubilee celebration in 1999. This special Issue of the IEEE Circuits and Systems Magazine is one of many celebrations and events planned this year by and for CASS members. The Celebrations not only reflect upon the history of our Society from multiple angles but also look forward to the future. The planning for this Special Issue started in July 2023 when Gabriele Manganaro, VP-Publications of IEEE CASS, tasked the incoming Editor-in-Chief (KP) to plan for the Special Issue. A Call for White Papers was issued to the CASS membership on 20 July 2023. The authors were asked to provide historical progress over the last 25 years and point out future directions for the next 25 years. We received numerous White Papers in September 2023, and were able to invite only few authors to submit Full Papers. Authors of Invited White Papers submitted their Full papers in second half of December 2023. All reviews were completed by March 2024. Before providing an overview of the papers in this Special Issue, we begin by thanking all the authors who took the time to submit the White Papers (whether Invited or not) and the Full papers. We are very grateful to all the reviewers who provided reviews in short notice due to the time constraints to publish the Special Issue.","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"30 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141058970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"NISQ Quantum Computing: A Security-Centric Tutorial and Survey [Feature]","authors":"Fan Chen, Lei Jiang, Hausi Müller, Philip Richerme, Cheng Chu, Zhenxiao Fu, Min Yang","doi":"10.1109/mcas.2024.3349665","DOIUrl":"https://doi.org/10.1109/mcas.2024.3349665","url":null,"abstract":"Quantum computing (QC) demonstrates substantial theoretical promise in addressing classically intractable problems. Recent investments and advancements across QC system stacks, including hardware, software, and algorithms, underscore a pivotal shift from theoretical exploration to the practical realization of applications. Despite this progress, the prevailing emphasis has predominantly centered on performance enhancement, often overlooking security considerations. In response to this gap, our article presents a comprehensive tutorial and survey aimed at identifying and categorizing vulnerabilities inherent in quantum computing systems. Beginning with an overview encompassing essential principles, ecosystem components, and unique attributes in the quantum computing system stack, we also provide a summary of development resources to facilitate efficient initiation in this domain. Building on this foundational knowledge, we introduce a taxonomy of QC security organized by victim layer and security attack objectives. Utilizing this taxonomy as a guiding framework, the article delivers an extensive survey of the latest advancements in QC security, with the overarching goal of equipping the reader with a comprehensive understanding of quantum computing system principles and an informed awareness of diverse and dynamic QC security threats. The intention is to benefit both industry stakeholders and research communities, ultimately aiming to proactively identify and mitigate security concerns within QC systems, thereby establishing a robust foundation for secure quantum computing environments.","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"30 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140071602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer-Scale Computing: Advancements, Challenges, and Future Perspectives [Feature]","authors":"Yang Hu, Xinhan Lin, Huizheng Wang, Zhen He, Xingmao Yu, Jiahao Zhang, Qize Yang, Zheng Xu, Sihan Guan, Jiahao Fang, Haoran Shang, Xinru Tang, Xu Dai, Shaojun Wei, Shouyi Yin","doi":"10.1109/mcas.2024.3349669","DOIUrl":"https://doi.org/10.1109/mcas.2024.3349669","url":null,"abstract":"Nowadays, artificial intelligence (AI) technology with large models plays an increasingly important role in both academia and industry. It also brings a rapidly increasing demand for the computing power of the hardware. As the computing demand for AI continues to grow, the growth of hardware computing power has failed to keep up. This has become a significant factor restricting the development of AI. The augmentation of hardware computing power is mainly propelled by the escalation of transistor density and chip area. However, the former is impeded by the termination of the Moore’s Law and Dennard scaling, and the latter is significantly restricted by the challenge of disrupting the legacy fabrication equipment and process. In recent years, advanced packaging technologies that have gradually matured are increasingly used to implement bigger chips that integrate multiple chiplets, while still providing interconnections with chip-level density and bandwidth. This technique points out a new path of continuing the increase of computing power while leveraging the current fabrication process without significant disruption. Enabled by this technique, a chip can extend to a size of wafer-scale (over 10,000 mm\u0000<inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$^{2}$ </tex-math></inline-formula>\u0000), provisioning orders of magnitude more computing capabilities (several POPS within just one monolithic chip) and die-to-die bandwidth density (over 15 GB/s/mm) than regular chips, and emerges a new Wafer-scale Computing paradigm. Compared to conventional high-performance computing paradigms such as multi-accelerator and datacenter-scale computing, Wafer-scale Computing shows remarkable advantages in communication bandwidth, integration density, and programmability potential. Not surprisingly, disruptive Wafer-scale Computing also brings unprecedented design challenges for hardware architecture, design- <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$backslash $ </tex-math></inline-formula>\u0000system- technology co-optimization, power and cooling systems, and compiler tool chain. At present, there are no comprehensive surveys summarizing the current state and design insights of Wafer-scale Computing. This article aims to take the first step to help academia and industry review existing wafer-scale chips and essential technologies in a one-stop manner. So that people can conveniently grasp the basic knowledge and key points, understand the achievements and shortcomings of existing research, and contribute to this promising research direction.","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"2 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140071599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Proceedings","authors":"","doi":"10.1109/mcas.2024.3361108","DOIUrl":"https://doi.org/10.1109/mcas.2024.3361108","url":null,"abstract":"","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"270 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140044894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Council on EDA and IEEE CASS [CAS in the World]","authors":"Ricardo Reis","doi":"10.1109/mcas.2024.3349670","DOIUrl":"https://doi.org/10.1109/mcas.2024.3349670","url":null,"abstract":"","PeriodicalId":55038,"journal":{"name":"IEEE Circuits and Systems Magazine","volume":"21 1","pages":""},"PeriodicalIF":6.9,"publicationDate":"2024-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140044907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}