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Journal of Electronic Testing-Theory and Applications最新文献

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Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams 利用Kronecker泛函决策图合成最近邻成本降低的可逆电路
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2022-02-01 DOI: 10.1007/s10836-022-05987-z
Dengli Bu, Junjie Yan, Pengjie Tang, Haohao Yuan
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引用次数: 1
2021 Reviewers 2021年的主持
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2022-01-01 DOI: 10.1007/s12529-022-10063-z
V. Krovi
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引用次数: 0
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration 通过运行时校准减少数字传感器的老化影响
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05976-8
Md Toufiq Hasan Anik, Mohammad Ebrahimabadi, J. Danger, S. Guilley, Naghmeh Karimi
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引用次数: 3
Editorial 社论
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05983-9
V. Agrawal
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引用次数: 0
2020 JETTA-TTTC Best Paper Award 2020年捷达tttc最佳论文奖
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05982-w
{"title":"2020 JETTA-TTTC Best Paper Award","authors":"","doi":"10.1007/s10836-021-05982-w","DOIUrl":"https://doi.org/10.1007/s10836-021-05982-w","url":null,"abstract":"","PeriodicalId":54841,"journal":{"name":"Journal of Electronic Testing-Theory and Applications","volume":"37 1","pages":"571 - 572"},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42168285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations 应用图表示法分析车载网络拓扑的安全漏洞级别
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05973-x
Zsombor Pethő, Intiyaz Khan, Arpad Torok
{"title":"Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations","authors":"Zsombor Pethő, Intiyaz Khan, Arpad Torok","doi":"10.1007/s10836-021-05973-x","DOIUrl":"https://doi.org/10.1007/s10836-021-05973-x","url":null,"abstract":"","PeriodicalId":54841,"journal":{"name":"Journal of Electronic Testing-Theory and Applications","volume":"37 1","pages":"613 - 621"},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46175498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement 重新测试有缺陷的电路以允许出现可接受的故障以提高产量
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05980-y
S. K. Jena, S. Biswas, J. Deka
{"title":"Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement","authors":"S. K. Jena, S. Biswas, J. Deka","doi":"10.1007/s10836-021-05980-y","DOIUrl":"https://doi.org/10.1007/s10836-021-05980-y","url":null,"abstract":"","PeriodicalId":54841,"journal":{"name":"Journal of Electronic Testing-Theory and Applications","volume":"37 1","pages":"633 - 652"},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49549292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Framework for Configurable Joint-Scan Design-for-Test Architecture 一种可配置联合扫描面向测试设计体系结构框架
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05978-6
Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh
{"title":"A Framework for Configurable Joint-Scan Design-for-Test Architecture","authors":"Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh","doi":"10.1007/s10836-021-05978-6","DOIUrl":"https://doi.org/10.1007/s10836-021-05978-6","url":null,"abstract":"","PeriodicalId":54841,"journal":{"name":"Journal of Electronic Testing-Theory and Applications","volume":"37 1","pages":"593 - 611"},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43674114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog 基于SystemVerilog的混合信号设计参数化实数模型
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-12-01 DOI: 10.1007/s10836-021-05977-7
Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos
{"title":"Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog","authors":"Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos","doi":"10.1007/s10836-021-05977-7","DOIUrl":"https://doi.org/10.1007/s10836-021-05977-7","url":null,"abstract":"","PeriodicalId":54841,"journal":{"name":"Journal of Electronic Testing-Theory and Applications","volume":"37 1","pages":"685 - 700"},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42682682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm 基于遗传算法的R-2R数模转换器测试生成方法
IF 0.9 4区 工程技术
Journal of Electronic Testing-Theory and Applications Pub Date : 2021-11-19 DOI: 10.1007/s10836-021-05974-w
Xiaoyan Yang, Chenglin Yang, Houjun Wang
{"title":"A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm","authors":"Xiaoyan Yang, Chenglin Yang, Houjun Wang","doi":"10.1007/s10836-021-05974-w","DOIUrl":"https://doi.org/10.1007/s10836-021-05974-w","url":null,"abstract":"","PeriodicalId":54841,"journal":{"name":"Journal of Electronic Testing-Theory and Applications","volume":"37 1","pages":"701 - 713"},"PeriodicalIF":0.9,"publicationDate":"2021-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46546693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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