2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

Parametric-Oscillation-Free Efficient SiGe:C Power Amplifier Design for Ku-/Ka-Band SATCOM 用于 Ku-/Ka 波段卫星通信的无参数振荡高效 SiGe:C 功率放大器设计

2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2024-01-21 DOI: 10.1109/SiRF59913.2024.10438545

Tsung-Ching Tsai, Václav Valenta, A. Cagri Ulusoy

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A 200 - 325 GHz Gain-Boosted J-Band Low-Noise Amplifier in a 130 nm SiGe BiCMOS Technology 采用 130 纳米 SiGe BiCMOS 技术的 200 - 325 GHz 增益增强型 J 波段低噪声放大器

2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2024-01-21 DOI: 10.1109/SiRF59913.2024.10438562

Manuel Koch, Sascha Breun, Robert Weigel

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SiRF 2024 Author Index SiRF 2024 作者索引

2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2024-01-21 DOI: 10.1109/sirf59913.2024.10438541

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CMOS LNA and VGA for 5G NR Using Gain-Linearity-Boosting and Body Floating Techniques 利用增益线性度提升和体浮技术实现 5G NR 的 CMOS LNA 和 VGA

2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2024-01-21 DOI: 10.1109/SiRF59913.2024.10438556

Jin-Fa Chang, Yo‐Sheng Lin

{"title":"CMOS LNA and VGA for 5G NR Using Gain-Linearity-Boosting and Body Floating Techniques","authors":"Jin-Fa Chang, Yo‐Sheng Lin","doi":"10.1109/SiRF59913.2024.10438556","DOIUrl":"https://doi.org/10.1109/SiRF59913.2024.10438556","url":null,"abstract":"We report a 9.5-mW 21.3-27.9-GHz CMOS low-noise amplifier (LNA) with auxiliary-gain-linearity-enhancement (AGLE) stage. It adopts body-floating and coupled-transmission-line (CTL)-based gain-boosting techniques. The LNA constitutes a common-source (CS) input stage, followed by CS gain and output stages. The bias current of the output stage is reused by the gain stage for low power dissipation ($mathrm{P}_{mathrm{dc}}$). The CTL in conjunction with a coupling capacitance $(C_{c t})$ contributes an in-phase gain at the output of the input stage. Over 21.3-27.9 GHz, 0.75-4.28 dB boosting in S21 and 0.25-0.46 dB reduction in noise figure (NF) are achieved. Moreover, based on the LNA topology, we report a 13.2mW 21-28-GHz CMOS variable-gain amplifier (VGA). Analog switch transistor M4 is in parallel with the output stage to tune its overdrive and drain-source voltage ($V_{D S}$) for fine tuning of S21. Digital switch transistor M5 is in parallel with the gain stage to control its $A C$ VDS for coarse tuning of S21. The VGA achieves S21 of 19.5 ± 1.5 dB for 21-28 GHz (i.e., 3-dB bandwidth $mathrm{f}_{3 mathrm{~dB}}=7 mathrm{GHz}$), S21 tuning range of 35.6 dB (21 ~ −14.6 dB), minimum NF of 1.99 dB at 24 GHz and average $mathrm{NF}(mathrm{NF}_{mathrm{avg}})$ of 2.19 dB for 21-28 GHz, and figure-of-merit (FOM2) of $61 mathrm{~nm} cdot mathrm{GHz}^{2 / 3} / mathrm{mW}^{1 / 3}$. The $mathrm{NF}_{text {avg}}$ and FOM2 are one of the best results ever reported for VGAs/LNAs with $f_{3 mathrm{~dB}}$ greater than 5 GHz and $P_{mathrm{dc}}$ lower than 15 mW.","PeriodicalId":518479,"journal":{"name":"2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"22 4","pages":"56-59"},"PeriodicalIF":0.0,"publicationDate":"2024-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Compact, High Tuning Accuracy and Enhanced Linearity 37-43 GHz Digitally-Controlled Vector Sum Phase Shifter 结构紧凑、调谐精度高、线性度更强的 37-43 GHz 数字控制矢量和相移器

2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2024-01-21 DOI: 10.1109/SiRF59913.2024.10438559

Mehran Hazer Sahlabadi, Hang Yu, J. Xia, S. Boumaiza

{"title":"A Compact, High Tuning Accuracy and Enhanced Linearity 37-43 GHz Digitally-Controlled Vector Sum Phase Shifter","authors":"Mehran Hazer Sahlabadi, Hang Yu, J. Xia, S. Boumaiza","doi":"10.1109/SiRF59913.2024.10438559","DOIUrl":"https://doi.org/10.1109/SiRF59913.2024.10438559","url":null,"abstract":"This paper presents a compact digitally controlled vector sum phase shifter (DC-VSPS) capable of precise gain and phase control across a wide bandwidth. The DC-VSPS utilizes a pair of differential variable gain amplifiers (VGAs) designed to optimize gain and phase tuning accuracy. Moreover, it incorporates differential transformers-based output combiner and input quadrature hybrid, enhancing integration, bandwidth, and matching performance. A 6-bit DC-VSPS prototype was successfully designed and fabricated using the 45 nm silicon-on-insulator (SOI) CMOS technology, occupying a minimal core area of $0.084 mathrm{~mm}^{2}$. Experimental results demonstrate an excellent tuning range of 360° for phase control with a resolution of 6 bits and 14 dB for gain control with 1 dB resolution. Furthermore, comprehensive measurements indicate excellent performance over the frequency range of 35-43 GHz, with total root-mean-square (RMS) phase error, total RMS gain error, and group delay variation all within 1.5°, 0.24 dB, and ±12 picoseconds, respectively. The prototype also exhibits input-referred 1dB gain compression power levels exceeding 4 dBm and input-output return losses better than 9 dB across the entire bandwidth.","PeriodicalId":518479,"journal":{"name":"2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"63 2","pages":"17-20"},"PeriodicalIF":0.0,"publicationDate":"2024-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low Phase Noise 104 GHz Oscillator Using Self-Aligned On-Chip Voltage-Tunable Spherical Dielectric Resonator in 130-nm SiGe BiCMOS 利用 130 纳米 SiGe BiCMOS 中的自对准片上电压可调球形介质谐振器实现 104 GHz 低相位噪声振荡器

2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2024-01-21 DOI: 10.1109/SiRF59913.2024.10438549

Yu Zhu, Georg Sterzl, Jan Hesselbarth, T. Meister, Frank Ellinger

{"title":"Low Phase Noise 104 GHz Oscillator Using Self-Aligned On-Chip Voltage-Tunable Spherical Dielectric Resonator in 130-nm SiGe BiCMOS","authors":"Yu Zhu, Georg Sterzl, Jan Hesselbarth, T. Meister, Frank Ellinger","doi":"10.1109/SiRF59913.2024.10438549","DOIUrl":"https://doi.org/10.1109/SiRF59913.2024.10438549","url":null,"abstract":"This paper studies a low phase noise voltage-controlled oscillator that is based on a self-aligned on-chip voltage-tunable spherical dielectric resonator. The proposed resonator has been designed for millimeter-wave applications, provides a high quality factor and is voltage controlled. To prove the concept, the circuit is implemented in a 130-nm SiGe BiCMOS technology. It consists of a two stage amplifier and a microstrip feedback path which couples to the resonator. Measurement results demonstrate a phase noise of −95.9 dBc/Hz at 10 MHz offset from the oscillation frequency at 104.03 GHz and a frequency tuning range of 88 MHz. A maximum output power of −9.9 dBm from 32.5 mW dc power is achieved. Simulations based on measurements of the on-chip spherical dielectric resonator indicate that circuit optimizations will lead to an excellent phase noise of −114.8 dBc/Hz at 10 MHz offset. To the best of the authors’ knowledge, this circuit is the first reported silicon-based MMIC voltage-controlled oscillator using an on-chip dielectric resonator at millimeter-wave band.","PeriodicalId":518479,"journal":{"name":"2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"23 2","pages":"83-86"},"PeriodicalIF":0.0,"publicationDate":"2024-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140531502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0