{"title":"A 41-GHz 19.4-dBm P<sub>sat</sub> CMOS Doherty power amplifier for 5G NR applications","authors":"Zheng Li, Zixin Chen, Qiaoyu Wang, Junqing Liu, Jian Pang, Atsushi Shirane, Kenichi Okada","doi":"10.1587/elex.20.20220558","DOIUrl":"https://doi.org/10.1587/elex.20.20220558","url":null,"abstract":"In this letter, a 41-GHz Doherty power amplifier (PA) in standard 65nm CMOS technology is introduced for 5G New Radio (NR) applications. The proposed PA implements the transformer-based parallel-combined Doherty structure to enhance the power-added efficiency (PAE). A tunable 90-deg hybrid coupler is proposed for output phase compensation. This work achieves a saturated output power (Psat) of 19.4dBm and an OP1dB of 18.6dBm at 41.5GHz under a 1-V power supply. The peak PAE and the PAE at 6-dB output power back-off (PBO) are 30.4% and 19.2%, respectively. This work also supports single-carrier mode (SC-mode) 400-MSymbols/s 256QAM and OFDMA-mode 400-MHz 256QAM. The core chip area is 0.22 mm2 with a static power consumption of 76mW.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136095419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yoshiki Hashimoto, Naoki Kaneda, K. Komoku, N. Itoh
{"title":"Study of 18.2-42.0 GHz Injection-Locked Frequency Doubler with Transformer Input","authors":"Yoshiki Hashimoto, Naoki Kaneda, K. Komoku, N. Itoh","doi":"10.1587/elex.20.20230107","DOIUrl":"https://doi.org/10.1587/elex.20.20230107","url":null,"abstract":"","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.8,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67301390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sampling circuit issues in A/D converters and challenges for the solution","authors":"A. Matsuzawa","doi":"10.1587/elex.20.20232001","DOIUrl":"https://doi.org/10.1587/elex.20.20232001","url":null,"abstract":"","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.8,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67302739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yunpeng Liu, Lin Lin, Shengjie Wang, Hongzheng Zeng
{"title":"An Ultra-wideband Tuning Method for Electrically Small Antenna Based on Characteristic Mode Analysis","authors":"Yunpeng Liu, Lin Lin, Shengjie Wang, Hongzheng Zeng","doi":"10.1587/elex.20.20230272","DOIUrl":"https://doi.org/10.1587/elex.20.20230272","url":null,"abstract":"","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.8,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67302774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhichao Zhang, Wenjie Zheng, Xinlin Xia, Yanjie Wang
{"title":"A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05 dBc reference spur and -245.9dB FOM in 40nm CMOS Technology","authors":"Zhichao Zhang, Wenjie Zheng, Xinlin Xia, Yanjie Wang","doi":"10.1587/elex.20.20230385","DOIUrl":"https://doi.org/10.1587/elex.20.20230385","url":null,"abstract":"This paper presents a 20.8-23.2GHz integer-N sub-sampling phase-locked loop (SSPLL) with low-reference spur and low-phase noise. A transformer-coupled based voltage controlled oscillator (VCO) is employed and its output is feedback as the input to SSPD in sub-sampling PLL to reduce the reference spur without requiring extra area and power consumption. In addition, a common source feedback circuit is adopted in the proposed sub-sampling charge pump (SSCP) to reduce current mismatch. The proposed sub-sampling PLL is implemented in a 40nm CMOS technology, measured results exhibit a frequency tuning range of 10.9% from 20.8 to 23.2GHz. The measured phase noise is -106.92@1MHz offset, the reference spur is -47.05 dBc. The typical power consumption is 29.1 mW from a 1.1V supply voltage, leading to a PLL FoM of -245.9 dB. The PLL occupies a core area of 1.2mm2.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135442758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An enhanced switching active disturbance rejection controller for speed control of permanent magnet synchronous motor","authors":"Peng Gao, Huihui Pan","doi":"10.1587/elex.20.20230476","DOIUrl":"https://doi.org/10.1587/elex.20.20230476","url":null,"abstract":"In this study, a novel active disturbance rejection controller (ADRC) is proposed to significantly improve the speed control performance of permanent magnet synchronous motor (PMSM). The conventional ADRC, namely linear active disturbance rejection controller (LADRC) and nonlinear active disturbance rejection controller (NLADRC), both them have their own merits and drawbacks. Thus, an enhanced switching active disturbance rejection controller (ESADRC) is developed to counteract the impacts of the speed-loop for the PMSM. The proposed ESADRC comprises several novel components including a novel tracking differentiator (TD), a novel switching extended state observer (SESO), a novel switching state error feedback (SSEF), and a cascaded extended state observer (ESO). The cascaded ESO is responsible for estimating the remaining disturbance after the SESO. Through comparative verification, it is verified that the proposed ESADRC outperforms the traditional ADRCs in terms of performance.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135710804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}