Journal of Systems Architecture最新文献

{"title":"MECSim: A comprehensive simulation platform for multi-access edge computing","authors":"Akhirul Islam,&nbsp;Manojit Ghose","doi":"10.1016/j.sysarc.2026.103706","DOIUrl":"10.1016/j.sysarc.2026.103706","url":null,"abstract":"<div><div>The rapid growth of CPU-intensive and latency-sensitive applications has intensified the need for efficient resource management within edge computing environments. While existing simulators such as iFogSim, EdgeCloudSim, and PureEdgeSim have contributed significantly to edge computing research, they lack comprehensive support for modeling modern hardware heterogeneity, energy-aware mechanisms, service providers’ economic models, dependent task modeling, and reliability-driven task management. This paper presents MECSim (multi-access edge computing simulator), an enhanced simulation framework that extends PureEdgeSim to enable realistic modeling of heterogeneous, cooperative, and fault-tolerant edge computing ecosystems. MECSim supports multi-data-center clusters along with dynamic voltage and frequency scaling (DVFS) capable user devices for energy-efficient operation. The framework further integrates dependent-task modeling, cost and profit evaluation for service providers, and reliability mechanisms via transient-failure simulation, caching, and task replication. We have implemented five state-of-the-art approaches, demonstrating the effectiveness of our simulation platform and building confidence in its practical utility to handle diverse system architectures. With its extensible architecture and comprehensive modeling capabilities, MECSim provides a promising platform for future research on energy-efficient, profit-driven, and fault-tolerant task offloading and scheduling in heterogeneous MEC environments. The results also demonstrate that MECSim achieves a 44.13% (on average) reduction in simulation time compared to EdgeCloudSim. In addition, we have conducted experiments using dispersion-aware metrics to quantify variability and stability across 50 independent runs, thereby enabling a more robust and reliable performance evaluation.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103706"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145981626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Data poisoning-based backdoor attacks against supervised learning rules of Spiking Neural Networks","authors":"Lingxin Jin ,&nbsp;Wei Jiang ,&nbsp;Jinyu Zhan ,&nbsp;Meiyu Lin ,&nbsp;Letian Chen ,&nbsp;Boran Quan ,&nbsp;Lin Zuo ,&nbsp;Xingzhi Zhou ,&nbsp;Maregu Assefa Habtie ,&nbsp;Naoufel Werghi","doi":"10.1016/j.sysarc.2026.103731","DOIUrl":"10.1016/j.sysarc.2026.103731","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs), known as the third generation neural networks, are developing rapidly and can compete with Artificial Neural Networks (ANNs) in many fields. However, the training environment of SNNs is similar to that of ANNs, which are highly dependent on open-source datasets, pre-trained models, and intelligent service platforms. Therefore, SNNs exposed to such an unregulated training environment are extremely vulnerable to backdoor attacks. Motivated by this, we investigate the feasibility of backdoor attacks on different supervised learning rules of SNNs and propose a universal attack framework based on data poisoning. The malicious operations only target the learnable stages in each learning rule, which rely on a data-driven method to inject backdoor information. Furthermore, we extended the backbone of the testing SNNs from a single-layer structure to deeper structures. Extensive experiments are conducted to evaluate the effectiveness of the attack framework, robustness, and backdoor migration phenomenon in SNN learning rules. Finally, we discuss potential countermeasures against backdoor attacks, corresponding technical challenges, and possible solutions.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103731"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146189647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Universally composable multi-factor authentication scheme for rail control systems","authors":"Xiaoya Hu ,&nbsp;Hao Zhang ,&nbsp;Ding Wang ,&nbsp;Zonghua Zhang ,&nbsp;Qingxuan Wang","doi":"10.1016/j.sysarc.2025.103670","DOIUrl":"10.1016/j.sysarc.2025.103670","url":null,"abstract":"<div><div>Rail transportation has emerged as a critical component of modern land transportation. With the development of informatization and intelligence, rail control systems have shifted from traditional closed environments to open networked environments. While interconnectivity offers operational benefits, it also exposes systems to severe security risks. As a safety-critical infrastructure, train operations rely on robust security mechanisms, among which user access authentication and train handover authentication are indispensable. However, despite the considerable research devoted to the latter, the former has been largely neglected. Moreover, although industry standards emphasize the deployment of multi-factor authentication (MFA) in industrial control systems or railway systems, no practical MFA scheme tailored for rail control systems has been developed. This gap stems from two challenges: (1) The inherent difficulty of designing protocols that can simultaneously withstand powerful adversaries and satisfy multiple security goals; (2) The deployment complexities arising from the heterogeneous, distributed, and large-scale nature of rail control systems, together with the large number of concurrently operating subsystems. To address these challenges, this paper analyzes two state-of-the-art MFA protocols and shows that neither ensures multi-factor security nor forward security. We then propose the <em>first</em> MFA scheme for rail control systems, built on a wireless sensor network architecture, and prove its security within the universal composability framework. A comparative evaluation with 68 representative MFA schemes reveals shows that our protocol achieves strong security. Furthermore, experiments performed on a laptop with an AMD Ryzen 7 5800H processor validate the high efficiency of the proposed scheme.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103670"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exact constrained-training neural networks for confidential 8-bit arithmetic primitives in code obfuscation","authors":"Ning Shi ,&nbsp;Lei Xu ,&nbsp;Tianqing Zhu ,&nbsp;WanLei Zhou ,&nbsp;Weizhi Meng ,&nbsp;Yu-an Tan","doi":"10.1016/j.sysarc.2026.103729","DOIUrl":"10.1016/j.sysarc.2026.103729","url":null,"abstract":"<div><div>Neural networks are rarely utilized for exact arithmetic computations. However, we aim to leverage them as accurate computing units in code obfuscation scenarios. The effectiveness of traditional code obfuscation methods is increasingly compromised by advanced reverse-engineering tools, which exploit the semantic transparency of arithmetic operations. To address this, we propose constrained-training neural networks tailored to 8-bit integer addition and multiplication, the most common operations in security-critical software. For addition, we introduce a constrained training algorithm that integrates weight clipping, linearity-enforcing loss terms, and boundary-case oversampling, enabling convergence to 100% accuracy across the entire domain. For multiplication, we design the adaptive symbol-gated NALU (ASG-NALU), an improved 4-bit multiplier that achieves exact results with reduced complexity. Combined with a cascade decomposition strategy, it extends to 8-bit multiplication with guaranteed correctness. Experiments confirm 100% in-domain accuracy, while out-of-domain inputs trigger catastrophic failures that act as natural traps, providing hidden security checks against dynamic analysis. These results establish exact constrained-training neural networks as confidential arithmetic primitives and firmly position neural arithmetic as a promising approach for advancing code obfuscation techniques.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103729"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"KVC-Q: A high-fidelity and dynamic KV Cache quantization framework for long-context large language models","authors":"Yusen Wu,&nbsp;Ruiqin Lin,&nbsp;Jiarong Que,&nbsp;Qixiang Zeng,&nbsp;Hongsen Zhang","doi":"10.1016/j.sysarc.2026.103699","DOIUrl":"10.1016/j.sysarc.2026.103699","url":null,"abstract":"<div><div>Large Language Models (LLMs) are increasingly powerful but face a significant memory bottleneck during long-context autoregressive inference due to the growing KV Cache. Existing uniform quantization methods for the KV Cache often neglect its dynamic and heterogeneous nature, leading to substantial performance degradation at low bit-widths. In this paper, we introduce KVC-Q, a novel framework that implements a dynamic, fine-grained quantization strategy. KVC-Q is built upon three core mechanisms: (1) Recency Priority, which preserves high precision for recent tokens; (2) Importance Preservation, which dynamically identifies and retains crucial long-term tokens in high fidelity; and (3) Head-Aware allocation, which assigns precision based on the sensitivity of different attention heads. Our experiments on the LongBench benchmark show that KVC-Q can reduce KV Cache memory footprint by approximately 70% (effectively competing with 4x compression methods) while retaining over 94% of the baseline performance, enabling models to process over 4x longer contexts on a single consumer-grade GPU. This work presents an effective and practical solution to mitigate the memory constraints of LLMs in long-context applications.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103699"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145981641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A PCM-based hybrid online learning architecture with adaptive threshold sign-based backpropagation and pulse-aware conductance control","authors":"Zhenhao Jiao ,&nbsp;Xiaogang Chen ,&nbsp;Tao Hong ,&nbsp;Shunfen Li ,&nbsp;Xi Li ,&nbsp;Weibang Dai ,&nbsp;Chengcai Tu ,&nbsp;Zhitang Song","doi":"10.1016/j.sysarc.2026.103683","DOIUrl":"10.1016/j.sysarc.2026.103683","url":null,"abstract":"<div><div>The increasing demand for low-latency, energy-efficient online learning in edge devices has driven the exploration of neuromorphic computing and hybrid analog–digital architectures. In this work, we propose a phase-change memory (PCM)-based hybrid architecture for in-situ online learning, which integrates parallel analog matrix–vector multiplication with adaptive digital control. The system features two key innovations: (1) an adaptive threshold sign-based backpropagation (ATSBP) algorithm that dynamically adjusts quantization thresholds for activations and error signals based on real-time feedback from mini-batch statistics, and (2) a pulse-aware conductance control scheme that enables precise conductance tuning of PCM devices using experimentally calibrated pulse-conductance mappings. These mechanisms jointly reduce unnecessary write operations and enhance robustness against device nonidealities such as nonlinearity and drift. Through systematic validation, we demonstrate that our hybrid architecture significantly improves convergence stability and energy efficiency in online learning scenarios, without sacrificing classification accuracy. The proposed system highlights a promising pathway toward scalable, hardware-friendly neuromorphic learning on edge platforms.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103683"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145981645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EdgeTrust-Shard: Hierarchical blockchain architecture for federated learning in cross-chain IoT ecosystems","authors":"Tuan-Dung Tran,&nbsp;Phuong-Dai Bui,&nbsp;Van-Hau Pham","doi":"10.1016/j.sysarc.2026.103701","DOIUrl":"10.1016/j.sysarc.2026.103701","url":null,"abstract":"<div><div>Enabling AI-driven real-time distributed computing on the edge-cloud continuum requires overcoming a critical dependability challenge: resource-constrained IoT devices cannot participate in Byzantine-resilient federated learning due to a 1940-fold memory gap, with robust aggregation methods demanding 512MB–2GB while microcontrollers offer only 264KB SRAM. We present EdgeTrust-Shard, a novel system architecture designed for dependability, security, and scalability in edge AI. It enables real-time Byzantine-resilient federated learning on commodity microcontrollers by distributing computational complexity across the network topology. The framework’s contributions include optimal <span><math><mrow><mi>M</mi><mo>=</mo><msqrt><mrow><mi>N</mi></mrow></msqrt></mrow></math></span> clustering for <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mi>N</mi><mo>)</mo></mrow></mrow></math></span> communication, a Multi-Factor Proof-of-Performance consensus mechanism providing quadratic Byzantine suppression with proven <span><math><mrow><mi>O</mi><mrow><mo>(</mo><msup><mrow><mi>T</mi></mrow><mrow><mo>−</mo><mn>1</mn><mo>/</mo><mn>2</mn></mrow></msup><mo>)</mo></mrow></mrow></math></span> convergence, and platform-optimized cryptography delivering a 3.4-fold speedup for real-time processing. A case study using a hybrid physical-simulation deployment demonstrates the system’s efficacy, achieving 93.9–94.7% accuracy across Byzantine attack scenarios at 30% adversary presence within a 140KB memory footprint on Raspberry Pi Pico nodes. By outperforming adapted state-of-the-art blockchain-FL systems like FedChain and BlockFL by up to 9.3 percentage points, EdgeTrust-Shard provides a critical security enhancement for the edge-cloud continuum, transforming passive IoT data sources into dependable participants in distributed trust computations for next-generation applications such as smart cities and industrial automation.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103701"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Orchestrating optimization passes of machine learning compiler for reducing memory footprints of computation graphs","authors":"Qianwei Yu ,&nbsp;Pengbo Nie ,&nbsp;Zihan Wang ,&nbsp;Chengcheng Wan ,&nbsp;Ziyi Lin ,&nbsp;He Jiang ,&nbsp;Jianjun Zhao ,&nbsp;Lei Qiao ,&nbsp;Le Chen ,&nbsp;Yuting Chen","doi":"10.1016/j.sysarc.2026.103694","DOIUrl":"10.1016/j.sysarc.2026.103694","url":null,"abstract":"<div><div>With the emergence of the needs of edge computing, there arises a demand for training and inferring deep learning (DL) models on memory-constrained devices. However, many DL models, namely computation graphs, have complex structure and plenty of parameters, incurring heavy memory consumption at runtime. Hence it is challenging but necessary to reduce their memory footprints at runtime.</div><div>This paper proposes <span>OPass</span>, a novel approach to perform hierarchical memory-constrained operator scheduling of machine learning models, and orchestrate optimization passes of Apache’s TVM (a machine learning compilation framework) for lowering memory footprints of computation graphs, finally allowing the graphs to run on memory-constrained devices. Firstly, given a computation graph <span><math><mi>G</mi></math></span>, <span>OPass</span> optimizes the graph heuristically and iteratively: <span>OPass</span> learns the effects of passes on the graph; it then optimizes <span><math><mi>G</mi></math></span> iteratively — each iteration picks up a pass by the reduction of the memory footprint of <span><math><mi>G</mi></math></span> and as well the implicit effects of the pass for further optimizations, letting the pass be applied. The second core component of <span>OPass</span> is its memory computation technique, named <span>OPass</span>Mem, which hierarchically schedules <span><math><mi>G</mi></math></span>’s operators. It constructs a hierarchical computation graph and employs an iterative scheduling algorithm to progressively reduce memory footprints.</div><div>We evaluate <span>OPass</span> on <span>ReBench</span> (a suite of computation graphs) and two real-world models (Transformer and ResNet). The results show the strength of <span>OPass</span>: it reduces up to 90.83% of graph’s memory footprints, outperforming TVM’s default by 2.34<span><math><mo>×</mo></math></span>. Specifically, pass orchestration and graph scheduling reduce memory footprints by up to 54.34% and 81%, respectively.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103694"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145941383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FP8ApproxLib: An FPGA-based approximate multiplier library for 8-bit floating point","authors":"Ruiqi Chen ,&nbsp;Yangxintong Lyu ,&nbsp;Han Bao ,&nbsp;Shidi Tang ,&nbsp;Jindong Li ,&nbsp;Yanxiang Zhu ,&nbsp;Ming Ling ,&nbsp;Bruno da Silva","doi":"10.1016/j.sysarc.2026.103686","DOIUrl":"10.1016/j.sysarc.2026.103686","url":null,"abstract":"<div><div>The 8-bit floating-point (FP8) data format has been increasingly adopted in neural network (NN) computations due to its superior dynamic range compared to traditional 8-bit integer (INT8). Nevertheless, the heavy reliance on multiplication in neural network workloads leads to considerable energy consumption, even with FP8, particularly in the context of FPGA-based deployments. To this end, this paper presents FP8ApproxLib, an FPGA-based approximate multiplier library for FP8. Firstly, we conduct a bit-level analysis of the prior approximation method and introduce improvements to reduce the resulting computational error. Based on these, we implement a fine-grained optimized design on mainstream FPGAs (Altera and AMD) using primitives and templates combined with physical layout constraints. Moreover, an automated tool is developed to support user configuration and generate HDL code. We then evaluate the accuracy and hardware efficiency of the FP8 approximate multipliers. The results show that our proposed method achieves an average error reduction of 53.15% (36.74%<span><math><mo>∼</mo></math></span>72.82%) compared to previous FP8 approximation method. Moreover, compared to prior 8-bit approximate multipliers, our FP8 designs exhibit the lowest resource utilization. Finally, we integrate the design into the inference phase of three representative NN models (CNN, LLM, and Diffusion), demonstrating its excellent power efficiency. This is the first FP8 approximate multiplier design with architecture-aware fine-grained optimization and deployment for modern FPGA platforms, which can serve as a benchmark for future designs and comparisons of FPGA-based low-precision floating-point approximate multipliers. The code of this work is available in our GitLab<span><math><msup><mrow></mrow><mrow><mo>∗</mo></mrow></msup></math></span>.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103686"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145981642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CAAS-DMSK: A Certificateless Anonymous Authentication Scheme with Dynamic Master Secret Keys in VANETs","authors":"Yan Xu,&nbsp;Huilan Zhang,&nbsp;Jie Cui,&nbsp;Hong Zhong","doi":"10.1016/j.sysarc.2026.103720","DOIUrl":"10.1016/j.sysarc.2026.103720","url":null,"abstract":"<div><div>Anonymous authentication can protect the communication security and vehicles’ identity privacy in Vehicular Ad Hoc Networks (VANETs). Certificateless authentication schemes eliminate the certificate management and key escrow problem, and several certificateless anonymous authentication schemes have been proposed for VANETs. In these schemes, the key generation center (KGC) and vehicles collaborate to generate the public/private key pairs. Although collaborative key generation between KGC and vehicles enhances security, both sides introduce critical vulnerabilities: vehicles independently generating public keys remain vulnerable to public key replacement (PKR) attacks, while KGC’s reliance on a static master secret key (MSK) in most schemes increases the risk of MSK leakage. Therefore, we propose a certificateless anonymous authentication scheme in VANETs, which is resistant to PKR attacks and supports dynamic MSK updating. The security analysis shows that the proposed scheme satisfies the security and privacy requirements of VANETs. Experimental results demonstrate that CAAS-DMSK reduces the computational costs by 41.53% in MSK updating.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"173 ","pages":"Article 103720"},"PeriodicalIF":4.1,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}