{"title":"Adaptive genetic algorithm based approach for evolutionary design and multi-objective optimization of logic circuits","authors":"Shuguang Zhao, Jianxun Zhao, L. Jiao","doi":"10.1109/EH.2005.7","DOIUrl":"https://doi.org/10.1109/EH.2005.7","url":null,"abstract":"Evolvable hardware is an artificial-evolution based promising path to automated design of circuits and discovery of fancy modules and principles. To improve gate-level evolution of logic circuits in speed and scale for synthetically optimized design results, an adaptive genetic algorithm based approach is presented in this paper. First, it employs an array-model-based encoding scheme that allows flexible changes of comprised logic cells' logic functions and interconnections. Second, it adopts a multi-objective fitness evaluation mechanism with weight-vector adapting and circuit simulation. Third, it features an adaptation strategy that enables crossover probability and mutation probability to vary with the individual diversity and the genetic process. By virtue of these measures, it was validated effective, efficient and innovative by some experiments on arithmetic circuits, in which we obtained functionally correct circuits with novel structures, fewer logic cells and higher operating speed as compared with results of some conventional or evolutionary approaches.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jorge Luís Machado do Amaral, Jose F. M. Amaral, R. Tanscheit, M. Pacheco, A. C. M. Filho
{"title":"Tuning evolvable PID controllers through a clonal selection algorithm","authors":"Jorge Luís Machado do Amaral, Jose F. M. Amaral, R. Tanscheit, M. Pacheco, A. C. M. Filho","doi":"10.1109/EH.2005.47","DOIUrl":"https://doi.org/10.1109/EH.2005.47","url":null,"abstract":"This work discusses the use of an evolvable proportional-integral-derivative (PID) controller that consists of a PID controller hardware whose gains can be set, for example, by evolutionary computation techniques, such as genetic algorithms. Due to PID controllers' widespread use in industry, tuning procedures for them are always a topic of interest. An evolutionary immune inspired algorithm, named clonal selection algorithm, is used for tuning the controller so that closed-loop step response specifications are satisfied. By using this procedure, designers need only specify the desired closed-loop response. Experiments with different processes indicate that the gains obtained through clonal selection algorithms may provide better responses than those obtained by the classical Ziegler-Nichols method. Moreover, the clonal algorithm is capable of generating adequate gains for systems where classical rules are not applicable.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127039588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hariri, R. Rastegar, K. Navi, M. S. Zamani, M. Meybodi
{"title":"Cellular learning automata based evolutionary computing (CLA-EC) for intrinsic hardware evolution","authors":"A. Hariri, R. Rastegar, K. Navi, M. S. Zamani, M. Meybodi","doi":"10.1109/EH.2005.12","DOIUrl":"https://doi.org/10.1109/EH.2005.12","url":null,"abstract":"Evolvable hardware (EHW) deals with the application of evolutionary algorithms in hardware design. In intrinsic EHW, the evolutionary algorithm or the fitness evaluation is implemented in hardware. In this case, there is a need for hardware-friendly algorithms. In this work, we introduce cellular learning automata based evolutionary computing (CLA-EC) as a new algorithm for intrinsic hardware evolution. The parallel structure of CLA-EC makes it suitable for EHW. Therefore, in this work we consider the application of this algorithm to EHW.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131581555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cross-domain features of runs of genetic programming used to evolve designs for analog circuits, optical lens systems, controllers, antennas, mechanical systems, and quantum computing circuits","authors":"J. Koza, Sameer H. Al-Sakran, L. W. Jones","doi":"10.1109/EH.2005.17","DOIUrl":"https://doi.org/10.1109/EH.2005.17","url":null,"abstract":"Genetic programming has now been successfully used to automatically synthesize human-competitive designs in a number of fields, including analog electrical circuits, optical lens systems, antennas, controllers, mechanical systems, and quantum computing circuits. Despite considerable variation in representation and technique, the above results share a number of common features. This paper identifies five common features and suggests possible explanations and interpretations for them. Some of these cross-domain observations clearly could not have been anticipated prior to the work being done.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An evolvable antenna platform based on reconfigurable reflectarrays","authors":"S. Hum, M. Okoniewski, R. J. Davies","doi":"10.1109/EH.2005.9","DOIUrl":"https://doi.org/10.1109/EH.2005.9","url":null,"abstract":"This paper presents an evolvable antenna architecture which allows the radiation pattern and gain of the antenna to be adapted in real time. The antenna can be implemented at a much lower cost than traditional antenna arrays, is simpler to construct, and is very robust. The architecture is also highly amenable to closed-loop control techniques that interface directly with the antenna hardware. A control scheme known as self-phasing was implemented using evolutionary algorithms and integrated with the antenna hardware. It enables the antenna to lock onto and track changes in incoming signal without any prior knowledge of the transmitter's location. It can also automatically reconfigure the antenna hardware to deal with environmental effects and faults in the array hardware. The design of a medium scale evolvable antenna system prototype is presented along with experimental results illustrating the retro-reflection capabilities of the antenna and controller.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127358541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A multi-objective genetic algorithm for on-chip real-time optimisation of word length and power consumption in a pipelined FFT processor targeting a MC-CDMA receiver","authors":"N. Sulaiman, T. Arslan","doi":"10.1109/EH.2005.4","DOIUrl":"https://doi.org/10.1109/EH.2005.4","url":null,"abstract":"This paper presents a multi-objective genetic algorithm for on-chip real-time optimisation of word length and power consumption in a fixed-point pipelined fast Fourier transform (FFT) processor targeting on MC-CDMA receiver. The multi-objective GA is used to find solutions for the FFT coefficients which have optimum performance in term of signal to noise ratio (SNR) and power consumption. The results demonstrate that the GA can find solutions which are optimised for both objectives. Results also show that there is a significant reduction in power consumption while maintaining the SNR after the optimisation. Optimisation from 16-bit to 11-bit, results in power reduction of 6.6% and an average error of 0.69 dB.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129462454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation results for a fault-tolerant multicellular architecture inspired by endocrine communication","authors":"Andrew J. Greensted, A. Tyrrell","doi":"10.1109/EH.2005.31","DOIUrl":"https://doi.org/10.1109/EH.2005.31","url":null,"abstract":"The hybrid redundancy structure found at the cellular level of higher animals provides complex organism with the three key features of a reliability-engineered system: fault tolerance, detection and recovery. For this reason, both the operation and organisation of this redundancy scheme provide an attractive source of inspiration for an electronic fault tolerant system. The electronic architecture documented within this paper models the cooperative operation and consequent fault masking of the multiple cells that form biological organs. A communication-system, inspired by endocrinology, is then used to network together these cells, coordinating their activity as organs, and controlling the operation of data processing tasks on a data stream. The bioNode hardware platform is used to implement and test the presented endocrinology inspired architecture. Results of the system's operation are provided to demonstrate the architecture's ability to maintain correct computation on. a data stream whilst being subjected to multiple and varied hardware faults.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embryonic machines that grow, self-replicate and self-repair","authors":"A. Stauffer, D. Mange, G. Tempesti","doi":"10.1109/EH.2005.20","DOIUrl":"https://doi.org/10.1109/EH.2005.20","url":null,"abstract":"After a reminder about embryonic machines endowed with universal construction and universal computation properties, this paper presents a novel architecture providing additional self-repairing capabilities. Based on the hardware implementation of the so-called Tom Thumb algorithm, the design of this machine leads to a new kind of cellular automaton made of a processing unit and a control unit. The corresponding hardware implementation results from a new and straightforward methodology for the design of self-replicating and self-repairing computing machines of any dimensions.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"83 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130874568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Move processor for bio-inspired systems","authors":"G. Tempesti, Pierre-André Mudry, R. Hoffmann","doi":"10.1109/EH.2005.3","DOIUrl":"https://doi.org/10.1109/EH.2005.3","url":null,"abstract":"The structure and operation of multi-cellular organisms relies, among other things, on the specialization of the cells' physical structure to a finite set of specific operations. If we wish to make the analogy between a biological cell and a digital processor, we should note that nature's approach to parallel processing is subtly different from conventional von Neumann architectures or even from conventional parallel processing approaches, where specialization is obtained by adapting software to a fixed hardware structure. In this article we present the outline of a novel processor architecture based on the Move or TTA (Transport-Triggered Architecture) approach. The features of such architectures allow them to implement systems that more closely resemble, within the limitations imposed by the capabilities of conventional silicon, the general modus operandi of multi-cellular organisms.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128813816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Femtocomputing: new architectural ideas for procedural and evolutionary computers whose components switch in femto-seconds","authors":"H. D. Garis, T. Batty, Wang Ce","doi":"10.1109/EH.2005.29","DOIUrl":"https://doi.org/10.1109/EH.2005.29","url":null,"abstract":"This paper presents some tentative ideas on how future procedural and evolutionary computers might compute, when nanotechnology gives us the possibility to store a bit of information on a single atom. At such tiny scales, switching times are likely to be in femtoseconds, i.e. quadrillionths of a second (Walls, 1994). Since electrical signals travel about 30 cm (a foot) in a nanosecond, a femtosecond will correspond to a millionth of this distance, i.e. a length of about 300 molecules. Traditional computing methodologies, using a centralized memory to store program instructions, and a centralized ALU to perform calculations, will no longer be appropriate, due to the time delays involved in fetching instructions from the program memory to the ALU. In the time this would take, the ALU would have changed its state (switching in femtoseconds). Hence both the program instructions and the means used to execute them, need to be distributed throughout the 3D space of the computational medium, whatever form it takes. This paper discusses new and preliminary architectural ideas on how \"femto-computers\" can compute in both a procedural and in an evolutionary style.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128863187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}