2005 NASA/DoD Conference on Evolvable Hardware (EH'05)最新文献_第2页

Non-evolvable indirectly replicating nanorobots with self-assembling parts 具有自组装部件的不可进化的间接复制纳米机器人

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.36

T. Toth-Fejel

引用次数: 0

Complexity metrics for self-monitoring impact sensing networks 自监测冲击传感网络的复杂性度量

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.14

M. Prokopenko, Peter Wang, D. Price

引用次数: 18

A case for using Minipop as the evolutionary engine in a CTRNN-EH control device: an analysis of area requirements and search efficacy 在CTRNN-EH控制装置中使用Minipop作为进化引擎的案例:对区域需求和搜索效果的分析

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.1

S. Vigraham, J. Gallagher

引用次数: 10

On evolution of relatively large combinational logic circuits 论大型组合逻辑电路的演化

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.37

E. Stomeo, T. Kalganova, Cyrille Lambert, N. Lipnitsakya, Y. Yatskevich

{"title":"On evolution of relatively large combinational logic circuits","authors":"E. Stomeo, T. Kalganova, Cyrille Lambert, N. Lipnitsakya, Y. Yatskevich","doi":"10.1109/EH.2005.37","DOIUrl":"https://doi.org/10.1109/EH.2005.37","url":null,"abstract":"Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128239262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Enabling the on-line intrinsic evolution of analog controllers 实现模拟控制器的在线内在演化

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.21

D. Gwaltney, M. I. Ferguson

引用次数: 3

On the robustness achievable with stochastic development processes 关于随机发展过程可实现的鲁棒性

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.38

S. Viswanathan, J. Pollack

引用次数: 3

Evolving assembly plans for fully automated design and assembly 为全自动设计和装配不断发展的装配计划

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.27

John Rieffel, J. Pollack

引用次数: 3

Autonomous FPGA fault handling through competitive runtime reconfiguration 通过竞争性运行时重构实现FPGA故障的自主处理

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.11

R. Demara, Kening Zhang

{"title":"Autonomous FPGA fault handling through competitive runtime reconfiguration","authors":"R. Demara, Kening Zhang","doi":"10.1109/EH.2005.11","DOIUrl":"https://doi.org/10.1109/EH.2005.11","url":null,"abstract":"An autonomous self-repair approach for SRAM-based FPGAs is developed based on competitive runtime reconfiguration (CRR). Under the CRR technique, an initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. At run-time, these individuals compete for selection based on a fitness function favoring fault-free behavior. Hence, any physical resource exhibiting an operationally-significant fault decreases the fitness of those configurations which use it. Through runtime competition, the presence of the fault becomes occluded from the visibility of subsequent FPGA operations. Meanwhile, the offspring formed through crossover and mutation of faulty and viable configurations are reintroduced into the population. This enables evolution of a customized fault-specific repair, realized directly as new configurations using the FPGA's normal throughput processing operations. Multiple phases of the fault handling process including detection, isolation, diagnosis, and recovery are integrated into a single cohesive approach. FPGA-based multipliers are examined as a case study demonstrating evolution of a complete repair for a 3-bit /spl times/ 3-bit multiplier from several stuck-at-faults within a few thousand iterations. Repairs are evolved in-situ, in real-time, without test vectors, while allowing the FPGA to remain partially online.","PeriodicalId":448208,"journal":{"name":"2005 NASA/DoD Conference on Evolvable Hardware (EH'05)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123291353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 53

A VHDL core for intrinsic evolution of discrete time filters with signal feedback 具有信号反馈的离散时间滤波器的内在演化的VHDL核心

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.6

D. Gwaltney, K. Dutton

引用次数: 11

Practical concerns when evolving circuits impervious to anticipated faults 当电路进化到不受预期故障影响时的实际问题

2005 NASA/DoD Conference on Evolvable Hardware (EH'05) Pub Date : 2005-06-29 DOI: 10.1109/EH.2005.39

G. Greenwood

引用次数: 0