2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)最新文献_第2页

Real-Time Efficient Detection in Vision Based Static Hand Gesture Recognition 基于视觉的静态手势识别的实时高效检测

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ISES.2018.00064

Amrutnarayan Panigrahi, J. P. Mohanty, A. Swain, K. Mahapatra

引用次数: 0

Design of CMOS Inverter and Chain of Inverters Using Neural Networks 基于神经网络的CMOS逆变器及逆变链设计

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ises.2018.00065

Likhit Valavala, Kalpit Munot, K. R. Teja

引用次数: 1

Smart Brewery Controller 智能啤酒厂控制器

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ises.2018.00052

Rolf Arne Kjellby, Erol Gorancic, Anders Liland, Linga Reddy Cenkeramaddi, Geir Jevne

引用次数: 0

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors 混合缓存对平铺芯片多处理器温度影响的分析

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ISES.2018.00021

Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, S. P. Mahajan, H. Kapoor

{"title":"Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors","authors":"Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, S. P. Mahajan, H. Kapoor","doi":"10.1109/ISES.2018.00021","DOIUrl":"https://doi.org/10.1109/ISES.2018.00021","url":null,"abstract":"Recent advances in CMOS technology adds more transistors to the chip that are utilised for improving processing capability by adding multiple processing components. These multiple cores raise the data demands leading to larger on-chip caches. Together, these add to the energy consumption as well as heat dissipation. Increase in chip temperature requires efficient cooling mechanisms as high temperatures can damage the onchip circuitry. Thus, the performance enhancement comes at the cost of higher power budget as well as temperature. Large onchip caches occupy significant area of the chip and are major contributors to leakage energy. It is known that as technology scales leakage becomes a prominent component which also affects the chip temperature. This paper aims to control the chip temperature by controlling the leakage energy dissipated by the last level caches (LLCs). Towards this we propose a hybrid LLC that uses a combination of SRAM cache banks and non-volatile memory (NVM) technology based STT-RAM banks. STT-RAM technology has the advantage of high density and low leakage.We demonstrate that low-leakage STT-RAM banks help in reducing the temperature of the tile in which they are located and it also assists in reducing the average chip temperature. Experimental evaluation on an isoarea and iso-capacity architecture that uses a hybrid LLC shows reduction the average chip temperature as well as gives gains in static energy and EDP compared to baseline architecture.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130613246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design and Prototype Implementation of Long-Range Self-Powered Wireless IoT Devices 远程自供电无线物联网设备的设计与原型实现

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ISES.2018.00054

Rolf Arne Kjellby, Linga Reddy Cenkeramaddi, Thor Eirik Johnsrud, Geir Jevne, Svein Erik Løtveit, B. Beferull-Lozano, Soumya Joshi

引用次数: 14

Crypto Primitives IPCore Implementation Susceptibility in Cyber Physical System 网络物理系统中密码原语IPCore实现的易感性

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ises.2018.00062

Dillibabu Shanmugam, S. Annadurai

引用次数: 0

ARPL: Supporting Adaptive Mixing of RPL Modes to Overcome Memory Overflow ARPL:支持自适应混合RPL模式以克服内存溢出

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ISES.2018.00035

Kunal Vyas, Jayasree Sengupta, S. Bit

{"title":"ARPL: Supporting Adaptive Mixing of RPL Modes to Overcome Memory Overflow","authors":"Kunal Vyas, Jayasree Sengupta, S. Bit","doi":"10.1109/ISES.2018.00035","DOIUrl":"https://doi.org/10.1109/ISES.2018.00035","url":null,"abstract":"IPv6 Routing Protocol for Low Power and Lossy Networks (RPL) proposed by Internet Engineering Task Force (IETF) has been adopted to suit Internet of Things (IoT) requirements. However, both the storing and non-storing modes of operation for RPL brings about certain limitations. In case of storing mode of RPL, if an intermediate node along the routing path overflows, new nodes become unreachable whereas, for the non-storing mode of RPL, the entire routing topology is only saved at the root node resulting in increased congestion near the root. Therefore, in this paper, we propose a low overhead Adaptive RPL (ARPL) algorithm which allows flexibility between storing and non-storing modes of operation. Here, the benefits of both the operating modes of RPL are utilized to avoid additional control message exchange, thereby making network resource-aware. We also observe that ARPL performs better than one state-of-the-art competitor in terms of storage and memory overflow by allowing the said flexibility of switching modes. Finally, we simulate ARPL using Cooja in Contiki operating system to evaluate the performance of ARPL. The simulation results show that ARPL achieves higher packet delivery ratio (PDR) in downward communication (e.g. query mode) while keeping convergence time same. It also shows that even in the mixed mode more than 90% nodes are operating in storing mode which improves Point to Point (P2P) communication with reduced traffic near the root thus allowing nodes to save energy.","PeriodicalId":447663,"journal":{"name":"2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131884347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Secure Biometric-Based Authentication Protocol for Vehicular Ad-Hoc Network 基于生物特征的车载Ad-Hoc网络安全认证协议

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ises.2018.00057

M. Ismail., Santanu Chatterjee, J. Sing

引用次数: 3

Performance Evaluation of Square Microhotplate with Alternative Membrane Materials 替代膜材料方形微热板的性能评价

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ISES.2018.00020

G. Saxena

引用次数: 0

Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores 基于编译驱动转换和模拟退火的DSP核容错优化方案

2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) Pub Date : 2018-12-01 DOI: 10.1109/ises.2018.00014

A. Sengupta, Deepak Kachave

引用次数: 0