发布求助
文献互助 智能选刊 最新文献

Proceedings. International Conference on Parallel Computing in Electrical Engineering最新文献

筛选
英文 中文
Verification of distributed systems modelled by high-level Petri nets 由高级Petri网建模的分布式系统的验证
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115202
V. Kozyura, V. Nepomniaschy, Ruslan M. Novikov
{"title":"Verification of distributed systems modelled by high-level Petri nets","authors":"V. Kozyura, V. Nepomniaschy, Ruslan M. Novikov","doi":"10.1109/PCEE.2002.1115202","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115202","url":null,"abstract":"A tool PNV (Petri net verifier) designed for analysis, modelling and verification of coloured Petri nets (CPN) is presented in the paper. The tool consists of two main components: a translator which generates an internal form of CPN and a C++ program modelling the input CPN, and a model-checking component which is applied to CPN limited by finite state systems when properties are presented in mu-calculus. Moreover, the translator generates a program in Pascal extended by a nondeterministic construct in order to model and verify the input CPN. The model-checking component uses the internal form of CPN and includes a model constructor which generates the reachability graph of CPN, and a model-checker. The paper describes a model-checking experiment with CPN which models the ring communication protocol (Cohen and Segall, 1991). An ineffectiveness of the ring protocol is proven by the experiment, and a modified effective ring protocol is verified too.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128964060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Architecture-to-task optimization system (ATOS) for parallel multi-mode data-flow architectures on a base of a partially reconfigurable computing platform 基于部分可重构计算平台的并行多模式数据流架构的架构到任务优化系统(ATOS)
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115192
F. Chayab, L. Kirischian, L. Szajek
{"title":"Architecture-to-task optimization system (ATOS) for parallel multi-mode data-flow architectures on a base of a partially reconfigurable computing platform","authors":"F. Chayab, L. Kirischian, L. Szajek","doi":"10.1109/PCEE.2002.1115192","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115192","url":null,"abstract":"This paper presents an approach of automated architecture synthesis for a wide class of parallel multi-mode data-flow embedded computing systems. This approach is based on the method of automated synthesis of multi-mode architectures. This method allows finding the best correspondence between a multi-mode data-flow application (task) and its parallel processing architecture. This method has been implemented in an architecture-to-task optimization system (ATOS) based on a partially reconfigurable computing platform (PRCP). It was estimated that ATOS could synthesize a complete architecture for an application presented in the form of a data-flow graph within a few seconds including emulation and performance measurements on the PRCP. The proposed approach can dramatically decrease the cost of the R&D design stage and time-to-market for a wide range of parallel multi-mode embedded computing systems.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"47 31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131681127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Systematic design of programs with sub-word parallelism 子字并行程序的系统设计
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115305
Rainer Schaffer, R. Merker, F. Catthoor
{"title":"Systematic design of programs with sub-word parallelism","authors":"Rainer Schaffer, R. Merker, F. Catthoor","doi":"10.1109/PCEE.2002.1115305","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115305","url":null,"abstract":"Upcoming processor generations increasingly provide instructions for sub-word parallelism. Thus, parallel execution of 2, 4 or 8 instructions (add, sub) or of complex instructions (sum of differences) with an input of 2, 4 or 8 operand pairs becomes possible. The exploitation of sub-word parallelism is still weakly supported by current compilers. To close this gap we present an approach to generate programs for processors with sub-word parallelism. To this end we adapt methods from the design of parallel processor arrays. An algorithm representing short term analysis filtering is used to illustrate the approach.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134285484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Multi-agent computing system in a heterogeneous network 异构网络中的多agent计算系统
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115252
P. Uhruski, M. Grochowski, R. Schaefer
{"title":"Multi-agent computing system in a heterogeneous network","authors":"P. Uhruski, M. Grochowski, R. Schaefer","doi":"10.1109/PCEE.2002.1115252","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115252","url":null,"abstract":"The paper presents the software platform that supports the activity of computational agents in a broad heterogeneous distributed computer environment. It is a set of software servers that support: agent's serialization and externalization; agent's sensors that examine the neighbouring machine resources; a migration mechanism enabling every agent to take an independent migration decision based on the current execution context; resource protection mechanisms including forcing agent migration and agent hibernation to disk. The platform prototype is deployed on Java Virtual Machine. The communication is realized by the CORBA framework. Sample work results and tests for the SBS parallel linear solver are provided and compared with the solver low-level, PVM version.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125059883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Comparative study of COW and SMP computer configurations COW和SMP计算机配置的比较研究
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115241
Gavril Godza, V. Cristea
{"title":"Comparative study of COW and SMP computer configurations","authors":"Gavril Godza, V. Cristea","doi":"10.1109/PCEE.2002.1115241","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115241","url":null,"abstract":"The class of MIMD parallel computers includes multiprocessor architectures, such as UMA, COMA, and NUMA, as well as multicomputer architectures, such as MPP and COW. Despite huge technological differences, machines with different architectures may be used to run certain similar applications. An interesting category of applications that may be successfully executed on a variety of parallel architectures is that of genetic algorithms (GAs) that provide more and more attractive solution of many complex engineering problems for which classical optimization methods cannot be used. GAs prove to be parallelizable in a natural way. Parallel genetic algorithms (PGAs) highlight good balance between calculations and communications that allows obtaining good results on different classes of parallel architectures. The paper describes the results obtained in a comparative study of PGAs, implemented on a cluster of SunBlade 100 workstations (COW) and on a Sun Enterprise E10000 (UMA) computer. The study demonstrates suitability of these different architectures for the development and execution of this class of applications. Also, some relevant facts concerning the performance of PGAs are presented.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125212912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Real-time scheduling in distributed systems 分布式系统中的实时调度
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115229
N. D. Thai
{"title":"Real-time scheduling in distributed systems","authors":"N. D. Thai","doi":"10.1109/PCEE.2002.1115229","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115229","url":null,"abstract":"Real-time computer systems are expected to greatly benefit from multiprocessor technology and employing multiprocessor systems for real-time applications has shown to be difficult. A major obstacle is that scheduling algorithms for real-time multiprocessor systems are significantly more complex than for uniprocessor systems. In multiprocessor systems, the scheduling algorithm must not only specify the order of tasks, but also determine the specific processor to be used. Any practical scheduling algorithm for assigning real-time tasks to a multiprocessor system presents trade-off between its computational complexity and its performance. Finding a minimal schedule for a given set of real-time tasks in a multiprocessor system has shown to be NP-hard. In this paper, we show several scheduling algorithms used in such multiprocessor systems and their performance with experimental results.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121381556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Irregular fine-grain parallel computing based on the slide register window architecture of Hitachi SR2201 基于日立 SR2201 滑动寄存器窗口架构的不规则细粒度并行计算
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115194
A. Smyk, M. Tudruj
{"title":"Irregular fine-grain parallel computing based on the slide register window architecture of Hitachi SR2201","authors":"A. Smyk, M. Tudruj","doi":"10.1109/PCEE.2002.1115194","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115194","url":null,"abstract":"In this article, an optimization method for parallelized execution of irregular fine grain computations is presented. This method was implemented using pseudo-vector processing (PVP) and sliding window register (SWR) mechanisms, which have been provided in Hitachi SR2201 supercomputer. The general idea of PVP and SWR relies on optimizing access to big continuous parts of memory and parallel execution of three kinds of operations placed in loops: loading and storing data, arithmetic operations. The main disadvantage of the above-mentioned mechanisms are that gain can be obtained only for long loops and regular expressions inside them. In our method, we focused attention on irregular computations, devoid of any predictable dependencies. We divided a given code into parts and manually optimized relations between loading and storing operations with taking into consideration the memory latency and delays in accessing needed data. In our implementation we obtained a speedup by using a simple reordering of sequences access operations to registers and memory.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130756977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Square interconnection network for data permutation 用于数据排列的方形互连网络
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115195
Zbigniew Kokosinski
{"title":"Square interconnection network for data permutation","authors":"Zbigniew Kokosinski","doi":"10.1109/PCEE.2002.1115195","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115195","url":null,"abstract":"In this paper a square cellular network for data permutation in a SIMD model is described. It has n/sup 2//4 2-permuters only, and realizes an arbitrary permutation pattern in two passes. For this network a programming algorithm is provided with O(n) sequential time complexity. Due to its regular cellular structure the square network is suitable for VLSI implementation.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128793589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Region-based Petri nets for modeling interrupts and cancellations 基于区域的Petri网建模中断和取消
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115203
J. Borkowski
{"title":"Region-based Petri nets for modeling interrupts and cancellations","authors":"J. Borkowski","doi":"10.1109/PCEE.2002.1115203","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115203","url":null,"abstract":"A synchronization mechanism using asynchronous activation and cancellation is considered. A process can receive asynchronous signals. The signals can either suspend the current activity causing the process to execute a handling procedure, or they can cancel the current computation. The Petri net formalism is employed to describe the behavior of the system. An extension to Color Petri Nets, region based PN, is proposed to model actions effecting a set of places while the exact marking is neither known nor important.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130593757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Verification of computations of a parallel FDTD algorithm 验证一个并行FDTD算法的计算
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115272
W. Walendziuk, J. Forenc
{"title":"Verification of computations of a parallel FDTD algorithm","authors":"W. Walendziuk, J. Forenc","doi":"10.1109/PCEE.2002.1115272","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115272","url":null,"abstract":"In the presented work the authors included the comparison of the calculations of a parallel FDTD algorithm with the computations obtained with the use of the Quick Wave programme published by QWED. The authors worked out a parallel implementation of the standard FDTD algorithm which is based on MPI communication library. The parallel algorithm was examined in a heterogeneous PC cluster.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117238062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信