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Proceedings. International Conference on Parallel Computing in Electrical Engineering最新文献

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Application of parallel hybrid algorithm in the optimization technique 并行混合算法在优化技术中的应用
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115286
A. Jordan, S. Ozawa, Marek Rulak
{"title":"Application of parallel hybrid algorithm in the optimization technique","authors":"A. Jordan, S. Ozawa, Marek Rulak","doi":"10.1109/PCEE.2002.1115286","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115286","url":null,"abstract":"The hybrid algorithm presented in the paper illustrates a coupling of the genetic algorithm method with the gradient method without constraints. The parallel implementation of a hybrid algorithm, which consists of the genetic algorithm and Gaussian elimination method is presented.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A number theoretical approach to the allocation problem of a pipelined dataflow model 对流水线数据流模型的分配问题提出了一些理论方法
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115239
Katalin Pásztor-Varga
{"title":"A number theoretical approach to the allocation problem of a pipelined dataflow model","authors":"Katalin Pásztor-Varga","doi":"10.1109/PCEE.2002.1115239","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115239","url":null,"abstract":"Let the result of the logic synthesis be a control data flow graph (CDFG) which is prepared to work as a pipeline system. If the restarting period (P) is given the next task is the optimization of the number of the functional elements. To decrease the number of functional elements either one functional element (processor) is allocated to more than one activity or a functional element (processor) is allocated to different activities. In both cases the common time functioning of the activities is examined as the basic data of the allocation algorithm. In this paper an approach of the allocation problem is shown. Here the base of the investigation is an ordered list of the modulo P regarded starting and end points of the transfer scores of the functional elements or activities in the CDFG. So a more effective algorithm is obtained for the normal data flow graph. The algorithm is extended to the graphs containing conditional branches.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129914574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of systolic computer Systola 1024 in image compression process in standard JPEG 2000 收缩期计算机Systola 1024在标准JPEG 2000图像压缩过程中的应用
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115336
S. Klimczak, M. Kwapisz, E. Lipowska-Nadolska
{"title":"Application of systolic computer Systola 1024 in image compression process in standard JPEG 2000","authors":"S. Klimczak, M. Kwapisz, E. Lipowska-Nadolska","doi":"10.1109/PCEE.2002.1115336","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115336","url":null,"abstract":"This paper presents a systolic realization of the discrete wavelet transform used in JPEG 2000 standard on Systola 1024 computer. A general idea of image compression, JPEG and JPEG 2000 standards, is explained.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130772527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Program execution control for communication on the fly in dynamic shared memory processor clusters 动态共享内存处理器集群中动态通信的程序执行控制
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115190
M. Tudruj, L. Masko
{"title":"Program execution control for communication on the fly in dynamic shared memory processor clusters","authors":"M. Tudruj, L. Masko","doi":"10.1109/PCEE.2002.1115190","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115190","url":null,"abstract":"The paper concerns efficient architectural solutions for shared memory systems composed of processor clusters based on busses. The essential proposed feature is program run-time dynamic switching of processors between clusters. A new communication paradigm, called communication on the fly is proposed, which is a combination of processor switching between clusters and parallel data reads of data from cluster busses to processor data caches. Specific data cache functionality is assumed in the system. Programs are decomposed into such tasks executed without preemption, so as to eliminate reloading of caches during task execution. A cache controlled program execution paradigm is proposed in which task execution is enabled only if all necessary data have been introduced to the processor data cache. An extended macro-data flow program graph representation is proposed for modeling functioning of data caches, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly useful for designing parallel programs for execution in the proposed architecture. This new program representation has been used for simulated symbolic execution of an FFT program graph, based on mapping of parallel tasks on dynamic SMP clusters with communication on the fly.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125573825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Automatic loop parallelization: an abstract interpretation approach 自动循环并行化:一种抽象解释方法
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115214
L. Ricci
{"title":"Automatic loop parallelization: an abstract interpretation approach","authors":"L. Ricci","doi":"10.1109/PCEE.2002.1115214","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115214","url":null,"abstract":"This paper presents an abstract interpretation to support the automatic parallelization of iterative constructs. The analysis approximates the range of values of any array subscript by integrating an interval analysis with one returning a set of simple linear restraints among program variables. To reduce the complexity of the analysis, a general methodology has been adopted that defines two different abstract domains, i.e. the interval domain and the bisector domain. The domains are then combined through the reduced product operator A static tool implementing the analysis has been automatically generated through PAG. The results of the analysis of kernel loops of the Perfect Club Benchmark are shown.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124529517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Associative parallel algorithms for computing functions defined on paths in trees 在树的路径上定义计算函数的关联并行算法
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115307
A. Nepomniaschaya
{"title":"Associative parallel algorithms for computing functions defined on paths in trees","authors":"A. Nepomniaschaya","doi":"10.1109/PCEE.2002.1115307","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115307","url":null,"abstract":"By means of an abstract model of the SIMD type with vertical data processing (the STAR-machine), we present a simple associative parallel algorithm for finding tree paths in undirected graphs. We study applications of this algorithm to update minimum spanning trees in undirected graphs, to determine maximum flow values in a multiterminal network, and to find a fundamental set of circuits with respect to a given spanning tree. These algorithms are given as the corresponding STAR procedures whose correctness is proved and time complexity is evaluated.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128469980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Parallel architectures and their development on the basis of intelligent solving machines 基于智能求解机的并行体系结构及其发展
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115191
V. Koval, Oleg N. Bulavenko, Z. Rabinovich
{"title":"Parallel architectures and their development on the basis of intelligent solving machines","authors":"V. Koval, Oleg N. Bulavenko, Z. Rabinovich","doi":"10.1109/PCEE.2002.1115191","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115191","url":null,"abstract":"The paper considers the creation of intelligent solving machines and the arrangement of parallel programming in intelligent distributed multiprocessor systems based on those. There are proposed some main concepts. A system is designed for programming in the C+Graph high-level language. C+Graph provides an efficient operation with knowledge (complicated data structures) and centralized-decentralized control exercised in virtually distributed computation space. Parallel C+Graph programming model is based on a model used for multiple-flow monoprocessor programming of the basic Java language. The model operates in a virtual C+Graph machine network. The ideology proposed can be considered as an efficient development of structural high-level language interpretation when applied to multi-microprocessor systems. Equipment structure of the basic version of intelligent solving machines is considered and some characteristics are discussed.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121553596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
SAR and thermal computations with the use of parallel FDTD algorithm SAR和热计算采用并行时域有限差分算法
Proceedings. International Conference on Parallel Computing in Electrical Engineering Pub Date : 2002-09-22 DOI: 10.1109/PCEE.2002.1115270
W. Walendziuk
{"title":"SAR and thermal computations with the use of parallel FDTD algorithm","authors":"W. Walendziuk","doi":"10.1109/PCEE.2002.1115270","DOIUrl":"https://doi.org/10.1109/PCEE.2002.1115270","url":null,"abstract":"In the following paper a two-dimensional parallel finite difference time-domain algorithm (FDTD) is presented. It uses a decomposition of a space domain into sub-areas. The shapes of the dielectrics are approximated by the groups of rectangles, described by coordinates. In addition, the parallel algorithm was equipped in the specific absorption rate and temperature increases calculation modules. The paper also contains the results of the efficiency research into two types of the connection topology of the computation nodes. The computations were made on a homogeneous cluster of personal computers.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"39 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114039650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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