{"title":"Systematic design of programs with sub-word parallelism","authors":"Rainer Schaffer, R. Merker, F. Catthoor","doi":"10.1109/PCEE.2002.1115305","DOIUrl":null,"url":null,"abstract":"Upcoming processor generations increasingly provide instructions for sub-word parallelism. Thus, parallel execution of 2, 4 or 8 instructions (add, sub) or of complex instructions (sum of differences) with an input of 2, 4 or 8 operand pairs becomes possible. The exploitation of sub-word parallelism is still weakly supported by current compilers. To close this gap we present an approach to generate programs for processors with sub-word parallelism. To this end we adapt methods from the design of parallel processor arrays. An algorithm representing short term analysis filtering is used to illustrate the approach.","PeriodicalId":444003,"journal":{"name":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. International Conference on Parallel Computing in Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PCEE.2002.1115305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Upcoming processor generations increasingly provide instructions for sub-word parallelism. Thus, parallel execution of 2, 4 or 8 instructions (add, sub) or of complex instructions (sum of differences) with an input of 2, 4 or 8 operand pairs becomes possible. The exploitation of sub-word parallelism is still weakly supported by current compilers. To close this gap we present an approach to generate programs for processors with sub-word parallelism. To this end we adapt methods from the design of parallel processor arrays. An algorithm representing short term analysis filtering is used to illustrate the approach.