2010 International Conference on Power, Control and Embedded Systems最新文献_第5页

Voltage sags and their characterization 电压跌落及其特性

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698628

Suryaprakash Singh, R. K. Tripathi

引用次数: 1

Power quality control of unregulated non-linear loads 非调节非线性负载的电能质量控制

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698627

R. K. Tripathi, C. P. Singh

{"title":"Power quality control of unregulated non-linear loads","authors":"R. K. Tripathi, C. P. Singh","doi":"10.1109/ICPCES.2010.5698627","DOIUrl":"https://doi.org/10.1109/ICPCES.2010.5698627","url":null,"abstract":"Increasing non-linear loads cause various undesirable effects and power quality problems on utility supply, like low system efficiency, poor power factor, derating of power supply equipments, disturbance to other consumers and interference in nearby communications networks etc. This work proposes a parallel power processing scheme to improve the power quality of uncontrolled diode bridge rectifier nonlinear loads. In this scheme a single phase synchronous link converter (SLC) is used as an auxiliary converter, in parallel to the diode bridge rectifier having DC capacitor supplying a resistive load, as main converter. Bulk amount of active power flows through the main converter; whereas the auxiliary converter takes care of the harmonics and reactive power requirement of main converter. A power transformer with 2:1 turn ratio is used at the input of the auxiliary converter in order to match the DC output voltages of two converters. The source current reference is derived using a PI controller which uses the output DC voltage feedback. The regulated output voltage is achieved using inner current control loop. The auxiliary converter current is controlled using HCC such as the summation of main and auxiliary converter input currents are sinusoidal and in phase with source voltage. A laboratory prototype experimental set-up with dedicated LabVIEW based controller is developed and tested in laboratory for experimentation. The simulation and experimental results obtained are in agreement.","PeriodicalId":439893,"journal":{"name":"2010 International Conference on Power, Control and Embedded Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Rational approximation of fractional operator — A comparative study 分数算子的有理逼近——比较研究

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698677

M. Khanra, J. Pal, K. Biswas

引用次数: 14

Multiphase sinusoidal oscillator with digital control 多相正弦振荡器与数字控制

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698632

M. S. Ansari

引用次数: 5

FPGA implementation of sine and cosine value generators using Cordic Algorithm for Satellite Attitude Determination and calculators 用Cordic算法FPGA实现正弦余弦值发生器用于卫星姿态确定和计算器

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698645

Shoaib Bhuria, P. Muralidhar

引用次数: 18

Impact of UPFC on distance relay: A case study UPFC对距离继电器的影响:一个案例研究

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698689

S. P. Pandey, M. Tripathy

引用次数: 2

Design and implementation of a programmable solar photovoltaic simulator 可编程太阳能光伏模拟器的设计与实现

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698650

Avneet Singh, A. Hota, A. Patra

引用次数: 18

Staircase modulated AC to AC converter 楼梯调制交流到交流转换器

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698660

Anshul Agarwal, V. Agarwal

引用次数: 10

Digital voltage-mode controller for soft-switching ZVT-ON boost converter 用于软开关ZVT-ON升压变换器的数字电压模式控制器

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5698656

M. Veerachary, Sachin Devassy

引用次数: 8

Ultra low voltage high speed 1-bit CMOS adder 超低电压高速1位CMOS加法器

2010 International Conference on Power, Control and Embedded Systems Pub Date : 2010-11-01 DOI: 10.1109/ICPCES.2010.5700479

Subodh Wairya, Himanshu Pandey, R. Nagaria, S. Tiwari

{"title":"Ultra low voltage high speed 1-bit CMOS adder","authors":"Subodh Wairya, Himanshu Pandey, R. Nagaria, S. Tiwari","doi":"10.1109/ICPCES.2010.5700479","DOIUrl":"https://doi.org/10.1109/ICPCES.2010.5700479","url":null,"abstract":"In this paper, we present a novel design for realize full adder circuit. Our approach based on XOR-XNOR design full adder circuits in a single unit. Objective of this work is to investigate the power, delay and power delay product of low voltage full adder cells in different CMOS logic styles. Simulation results illustrate the superiority of the proposed adder circuit against the conventional CMOS, Hybrid, Bridge, Xor-Xnor adder circuits in terms of power, delay, PDP. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. The performance of the full adder circuits is based on GPDK 90nm CMOS process models at all range of the supply voltage starting from 0.65V to 1.5V evaluated by the comparison of the simulation results obtained from Cadence. Simulation results reveal that the proposed circuit exhibits lower PDP and is faster when compared with available 1-bit full adder circuits. To summarize, some performance criteria are considered in the design and evaluation of adder cells, of which some are at ease of design, robustness, silicon area, delay, and power consumption. The design is implemented on GDPK 90 nm process models in Cadence Virtuoso Schematic Composer at 1.5V single ended supply voltage and simulations are carried out on Spectre S.","PeriodicalId":439893,"journal":{"name":"2010 International Conference on Power, Control and Embedded Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114110251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25