超低电压高速1位CMOS加法器

Subodh Wairya, Himanshu Pandey, R. Nagaria, S. Tiwari
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引用次数: 25

摘要

本文提出了一种实现全加法器电路的新设计。我们的方法基于XOR-XNOR在单个单元中设计全加法器电路。本工作的目的是研究不同CMOS逻辑风格的低压全加法器单元的功率、延迟和功率延迟积。仿真结果表明,所提出的加法器电路在功率、延迟、PDP等方面优于传统的CMOS、混合、桥接、异或异或加法器电路。这种桥式设计方式通过使用一些被称为桥式晶体管的晶体管,具有比传统CMOS设计方式更规整、密度更高、功耗更低的特点。完整加法电路的性能基于GPDK 90nm CMOS工艺模型,在电源电压从0.65V到1.5V的所有范围内进行评估,并与Cadence获得的仿真结果进行比较。仿真结果表明,与现有的1位全加法器电路相比,该电路具有更低的PDP和更快的速度。综上所述,在加法器单元的设计和评估中考虑了一些性能标准,其中一些是易于设计,鲁棒性,硅面积,延迟和功耗。该设计在Cadence Virtuoso Schematic Composer中的GDPK 90 nm制程模型上实现,单端电源电压为1.5V,并在Spectre S上进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Ultra low voltage high speed 1-bit CMOS adder
In this paper, we present a novel design for realize full adder circuit. Our approach based on XOR-XNOR design full adder circuits in a single unit. Objective of this work is to investigate the power, delay and power delay product of low voltage full adder cells in different CMOS logic styles. Simulation results illustrate the superiority of the proposed adder circuit against the conventional CMOS, Hybrid, Bridge, Xor-Xnor adder circuits in terms of power, delay, PDP. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. The performance of the full adder circuits is based on GPDK 90nm CMOS process models at all range of the supply voltage starting from 0.65V to 1.5V evaluated by the comparison of the simulation results obtained from Cadence. Simulation results reveal that the proposed circuit exhibits lower PDP and is faster when compared with available 1-bit full adder circuits. To summarize, some performance criteria are considered in the design and evaluation of adder cells, of which some are at ease of design, robustness, silicon area, delay, and power consumption. The design is implemented on GDPK 90 nm process models in Cadence Virtuoso Schematic Composer at 1.5V single ended supply voltage and simulations are carried out on Spectre S.
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