The Sixth International Conference on VLSI Design最新文献_第3页

High Level Design Experiences With Ideas 具有高层次的设计经验和创意

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669655

C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer

引用次数: 0

A Methodology for Generating Application Specific Tree Multipliers 生成特定于应用程序的树乘数的方法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669673

S. Ramanathan, N. Mohanty, V. Visvanathan

引用次数: 1

An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis 数据路径综合中调度、模块分配和绑定的集成加速ILP解决方案

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669676

T. C. Wilson, N. Mukherjee, M. Garg, D. Banerji

引用次数: 10

Design of an on-line Euclidian Processor 在线欧几里德处理器的设计

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669632

R. Bouraoui, A. Guyot, G. Walker

引用次数: 1

NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs NPCPL:用于低延迟、高吞吐量设计的正常工艺互补通型晶体管逻辑

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669707

D. Ghosh, S. Nandy, K. Parthasarathy, V. Visvanathan

引用次数: 14

Hardware Algorithms for Polygon Matching 多边形匹配的硬件算法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669635

R. Sastry, N. Ranganathan, H. Bunke

引用次数: 3

Fault-Tolerant Arbitration in Multichip Crossbar Switches 多片交叉交换机中的容错仲裁

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669709

Joydeep Ghosh, N. Krishnamurthy

引用次数: 3

A Partition Approach to Find the Length of the Longest Common Subsequence 一种求最长公共子序列长度的划分方法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669631

Chowdhury S. Rahman, Mi Lu

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引用次数: 1

Efficient Technique to Reduce Gate Evaluations and Speed up Fault Simulation 减少栅极评估和加速故障模拟的有效技术

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669650

P. R. S. Kumar, M. Srinivas, J. Jacob

引用次数: 2

Algorithm-Based Concurrent Error Detection for FFT Networks 基于算法的FFT网络并发错误检测

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669667

C. Oh, H. Youn, V. K. Raj

引用次数: 26