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The Sixth International Conference on VLSI Design最新文献

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Harmonic Scheduling: A Technique for Scheduling beyond Loop-Carried Dependencies 调和调度:一种超越环携带依赖的调度技术
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669677
Haigeng Wang, N. Dutt, A. Nicolau
{"title":"Harmonic Scheduling: A Technique for Scheduling beyond Loop-Carried Dependencies","authors":"Haigeng Wang, N. Dutt, A. Nicolau","doi":"10.1109/ICVD.1993.669677","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669677","url":null,"abstract":"Loop-Carried Dependencies (LCDs) are ubiquitous in behaviors that describe recurrences. Effective parallelization and scheduling of behaviors involving recurrences is a difficult task but is crucial for several real-time high-performance applications such as DSP. We present a novel approach, Harmonic Scheduling, that exploits the parallelism in these recurrences beyond LCDs and which generates optimal schedules for parallel evaluation of linear difference equations with resource constraints. Based on this approach, we then formulate the problem of and give an algorithm for finding optimal schedules for linear difference equations under more realistic constraints: using a fixed number of adders and multipliers that have different execution times.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131263112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Integrated Technology CAD System for Process and Device Designers 工艺与设备设计集成技术CAD系统
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669698
K. S. V. Gopalarao, P. K. Mozumder, D. Boning
{"title":"An Integrated Technology CAD System for Process and Device Designers","authors":"K. S. V. Gopalarao, P. K. Mozumder, D. Boning","doi":"10.1109/ICVD.1993.669698","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669698","url":null,"abstract":"A workstation-based integrated system with a highly interactive X/Motif user interface is discussed. At present, TSUPREM3, TSUPREM4 and TPISCES have been integrated into this system. The components of the integrated TCAD system include a generic process recipe editor, a mask editor, a 2-D wafer structure builder (using 1-D/2-D process simulation profiles), a mesh generator for 2-D device simulation, a device simulation recipe editor, and graphical postprocessors for both process and device analysis. The user of this system inputs the specification of a process recipe and the layout of the device structure to be fabricated. The system then runs process and device simulation using incremental and shared simulation strategies to generate wafer structure and electrical device characteristics. An interactive user interface guides the user through the process and device simulation flow. thereby aiding what-if analysis of process and device tradeoffs. >","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131643485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On Unified Delay Fault Testing 论统一延迟故障检测
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669694
A. Pramanick, S. Reddy
{"title":"On Unified Delay Fault Testing","authors":"A. Pramanick, S. Reddy","doi":"10.1109/ICVD.1993.669694","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669694","url":null,"abstract":"The field of delay fault testing has traditionally been dichotomous in that two different fault models, path delay faults and gate delay faults, have received extensive attention. In this paper, we present a unified approach to testing for both fa& models (not to be confused with testing for hybrids of these two). We formally show how general robust tests for path delay faults can be used as high quality single gate delay fault tests, and how such tests greatly simplib the computations of fault sizes detected, over previous methods. A method to assure full covc’rage under the single gate delay fault model in such circuits is given, where the robust tests employed need not be of any special class.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Statistical Analysis of Controllability 可控性统计分析
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669638
Amitava Majumdar, S. Sastry
{"title":"Statistical Analysis of Controllability","authors":"Amitava Majumdar, S. Sastry","doi":"10.1109/ICVD.1993.669638","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669638","url":null,"abstract":"","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114884756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Minimization of Logic Functions using essential Signature Sets 使用本质签名集的逻辑函数的最小化
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669704
P. McGeer, J. Sanghavi, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Minimization of Logic Functions using essential Signature Sets","authors":"P. McGeer, J. Sanghavi, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICVD.1993.669704","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669704","url":null,"abstract":"We present a new algorithm for exact two-level logic optimization. It differs from the classical approach; rather than generating the set of all prime implicants of a function, and then deriving a covering problem, we derive the covering problem directly and implrcitly, and then generate only those primes involved in the covering problem. We represent a set of primes by the cube of their intersection. The set of sets of primes which forms the covering problem is unique. Hence the corresponding set of cubes forms a canonical coaer. We give a successive reduction algorithm for finding the canonical cover from any initial covw, ‘we then generate only those primes involved in at least one minimal cover. The method is effective; solutions for 10 of the 20 hard examples in the ESPRESSO benchmark set are derived and proved minimum. For 5 of the remaining examples the canonzcad cover is derivrBd, but the covering problem remains to be solved exactly.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129572024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits 监控自检顺序电路最优设计的状态分配
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669627
R. Parekhji, G. Venkatesh, S. Sherlekar
{"title":"State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits","authors":"R. Parekhji, G. Venkatesh, S. Sherlekar","doi":"10.1109/ICVD.1993.669627","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669627","url":null,"abstract":"iment for Optimal Design of Monitored Self-checking Sequential Circuits 12. A. Parelrhji G. Venkatesh S .D. Sherlekar Department of Computer Science & Engineering Indian Institute of Technology, Bombay 400076, INDIA T h i s paper addresses the issue of s tate assignment f o r self-checking sequential circuits implemented using the mon i tor ing m a c h i n e approach. It is shown how perf o r m i n g appropriaie s tate assignment significantly reduces the cost of imp lemen t ing such circuits. A n e w heuris t ic method f o r s tate assignment called CUBIC is proposed. It i s based o n embedding the s tate t rans i t i on graph of t he g i ven FSM in a n appropriate subspace of a hypercube, so as t o m i n i m i s e a variant of t he dilat i o n cost f unc t ion . Per forming s tate as s ignmen t using C U B I C f o r a numrber o,F real examples shows tha t i t n o t only reduces the cost of the mon i tor ing mach ine , bu,t also results in 12 small-sized imp lemen ta t ion of t he m a i n mach ine .","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Delay Fault Test Generation with Cellular Aulhomata 基于元胞自拟的延迟故障测试生成
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669697
Sukumar Nandi, V. Boppana, Supratik Chakraborty, P. P. Chaudhuri, Samir Roy
{"title":"Delay Fault Test Generation with Cellular Aulhomata","authors":"Sukumar Nandi, V. Boppana, Supratik Chakraborty, P. P. Chaudhuri, Samir Roy","doi":"10.1109/ICVD.1993.669697","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669697","url":null,"abstract":"Two-patterns are required to test the delay faults within a circuit. Cellular Automata (CA) has been proposed as a two-pattern generator in the present work. A simple method for obtaining the phase shift between various CA stages has been investigated. A lower bound of number of CA cells required and algorithms for finding the best CA for a given pattern set are also presented.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131062354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
MHPS-Driven Early Design and Analysis of VLSI CPU Chips mhps驱动的VLSI CPU芯片早期设计与分析
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669691
P. Bose, J. Wellman
{"title":"MHPS-Driven Early Design and Analysis of VLSI CPU Chips","authors":"P. Bose, J. Wellman","doi":"10.1109/ICVD.1993.669691","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669691","url":null,"abstract":"JVe present (1 noid appsoaclz to carry per/i,rinancc analysis arid tiiiiitig of VLSI processors, don(? in the context of higlt-lewl source Iceriicls. U7e illustrate our rnetliodology in 1Crt71.r of a small (exaniph?) super scalas RlSC J ~ S O C ~ S S I ~ S architecture. A pnrantetrized execution 17ic~cIeI is used fhr piforinance eslimniion. IJsing an iterative optimization techniqire, the parameter set can bc locally optiinizcd around a g i i w design point to genesare tlie ininii?itrtn cycles per. iiwtrttction ( V I ) . W e also iiicludc a ctirsory discussion on linking .rirclt a CI’I estiiizntor io an early jloorplanner jhr A f IPS-driven block layout for the processor chb.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129207413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesis of Sequential Circuits for Robust Path Delay Fault Testability 鲁棒路径延迟故障可测性序列电路的综合
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669696
S. Bhatia, N. Jha
{"title":"Synthesis of Sequential Circuits for Robust Path Delay Fault Testability","authors":"S. Bhatia, N. Jha","doi":"10.1109/ICVD.1993.669696","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669696","url":null,"abstract":"In this paper, we show how to synthesize sequential circuits for hazard-free robust path delay fault testability using a method called synthesis for parallel scan. Utilizing a new clocking scheme and a previous method for synthesizing completely robustly testable combinational circuits, we first show how complete (i.e. 100%) robust testalsility of sequential circuits can be guaranteed without using enhanced scan, when the number of primary inputs and primary outputs of the sequential circuit is each at least as large as the number of latches. This condition is met by many, but not all, sequential circuits. However, no previous method could guarantee complete robust testability of all path delay faults in a sequential circuit without assuxning complete enhanced scan. When the number of outputs is less (but the number of inputs is more) than the number of latches, we can ensure high, but not necessarily coimplete, robust testability, although for all the benchmarks we considered we did obtain 100% robust testability. For all these methods we only need non-scan, normal latches. The area overheads are relatively small.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123112407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Self-organisation and its application to binding 自组织及其在绑定中的应用
The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669675
A. Hemani
{"title":"Self-organisation and its application to binding","authors":"A. Hemani","doi":"10.1109/ICVD.1993.669675","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669675","url":null,"abstract":"This paper presents Kohonen's self-organi- sation algorithm as an optimisation tool. Its application is illustrated by applying it to a high-level synthesis(HLS) problem - binding: the task of assigning operations to spe- cijic instances of functional units. It is a crucial problem, as it injluences the interconnect, wiring and register cost. This Self-Organising Binder (SOB) has a built-in hill- climbing mechanism, and being based on neural-network it can be easily parallelised. We apply SOB to benchmark examples and show that the results are comparable to the best reported in the field.","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116231145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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