The Sixth International Conference on VLSI Design最新文献

Modular Design Methodologies For Image Processing Architectures 图像处理体系结构的模块化设计方法

The Sixth International Conference on VLSI Design Pub Date : 1993-12-01 DOI: 10.1109/ICVD.1993.669692

A. Antola, A. Avai, L. Breveglieri

引用次数: 4

DESSERT: Design Space Exploration of RT Level Components 甜点:RT级组件的设计空间探索

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669700

M. V. Rao, M. Balakrishnan, Anshul Kumar

引用次数: 5

Greedy Hardware Optimization For Linear Digital Systems Using Number Splitting And Repeated Factorization 基于数字分裂和重复分解的线性数字系统贪婪硬件优化

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669669

A. Chatterjee, R. Roy, M. d'Abreu

引用次数: 10

GB: A New Grid-Based Binding Approach for High-Level Synthesis 基于网格的高阶合成绑定新方法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669674

Hyuk-Jae Jang, B. Pangrle

引用次数: 3

BEST: Bond editor and test vector translator 最佳:Bond编辑器和测试向量翻译器

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669656

P. Marimuthu, K. Raghunathan

引用次数: 1

Estimating Area Efficiency of Antifuse based Channeled FPGA Architectures 基于抗熔断的信道FPGA结构面积效率估计

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669649

M. Mehendale, K. Roy

引用次数: 1

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic 多层无狗腿通道路由的np完备性及一种有效的启发式算法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669643

R. Pal, S. P. Pal, A. Pal, Alak K. Dutta

引用次数: 9

A Parallel VLSI Circuit Layout Methodology 一种并行VLSI电路布局方法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669686

S. Bapat, J. Cohoon

引用次数: 10

Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach 模拟集成电路测试计划的自动生成-一种实用方法

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669665

R. Naiknaware, G. Nandakumar, R. Arora, J. Larkin

引用次数: 2

A Scheme For Synthesizing Testable Vlsi Designs With Minimum Area Overhead 一种以最小面积开销合成可测试Vlsi设计方案

The Sixth International Conference on VLSI Design Pub Date : 1993-01-03 DOI: 10.1109/ICVD.1993.669657

B. Mitra, P. P. Chaudhuri

{"title":"A Scheme For Synthesizing Testable Vlsi Designs With Minimum Area Overhead","authors":"B. Mitra, P. P. Chaudhuri","doi":"10.1109/ICVD.1993.669657","DOIUrl":"https://doi.org/10.1109/ICVD.1993.669657","url":null,"abstract":"In contrast to conventional design and test approaches where testability is considered after the design phase, the scheme presented here selects efficient test configurations in the ear& stages of design synthesis. The integrated appmach presented here aims at arriving at a synthesized design with minimum area overhead. THE SCHE ME Theschemetakesaslnput, adataflow graph (DFG) (derived from a VHDL description) that serves as the input to the datapath synthesis system. Given a DFG, we have used a stochastic evolution [l J based optimization scheme for simultaneous scheduling, allocation and binding of the datapath architecture. The first step in this procedure is the creationof a resource-control step matrix from the DFG. A Finite State Machine (FSM) description for controlling this datapath is next generated from the original VHDL description and the datapath architecture being evaluated. In view ofthe high computational complexity associatedwith synthesizingthe FSM at every iteration, we have developed a scheme to estimate the complexity of the control logic directly [2] from the FSM spedfications. The stochastic evolutionscheme incorporates test synthesis procedures in every iteration of the optimization step to ensure that a datapath architecture is finally selected which is not only testable, but forwhich the total area (includingthe test area overhead) is minimum. Since most test synthesis systems described in the past are extremely computation intensive, applying these in the optimization loop of stochastic evolution has been found to be very ineffident. Instead, we have developed several efficient heuristics for test synthesis that configures the candidatedatapatharchaecturesfortest. The test area overhead associated with every such candidate architecture is determined by adding the","PeriodicalId":439235,"journal":{"name":"The Sixth International Conference on VLSI Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0