2008 International Symposium on Industrial Embedded Systems最新文献

Dynamic voltage and frequency scaling for optimal real-time scheduling on multiprocessors 多处理器上最优实时调度的动态电压和频率缩放

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577677

Kenji Funaoka, Akira Takeda, S. Kato, N. Yamasaki

引用次数: 25

Implementation of an efficient RDMA mechanism tightly coupled with a TCP/IP offload engine 实现了与TCP/IP卸载引擎紧密耦合的高效RDMA机制

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577684

Hankook Jang, Sang-Hwa Chung, Dae-Hyun Yoo

{"title":"Implementation of an efficient RDMA mechanism tightly coupled with a TCP/IP offload engine","authors":"Hankook Jang, Sang-Hwa Chung, Dae-Hyun Yoo","doi":"10.1109/SIES.2008.4577684","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577684","url":null,"abstract":"We develop a hybrid TCP/IP offload engine (hybrid TOE) that processes TCP/IP via hardware/software coprocessing based on an FPGA and a general-purpose embedded processor. We also develop an efficient remote direct memory access (RDMA) mechanism that is tightly coupled with the hybrid TOE. In this mechanism, the hybrid TOE performs CRC calculations using hardware modules and supports zero-copy data transmission; the host CPU simply generates and processes RDMA protocol headers. By using the hybrid TOE and the RDMA mechanism, computer systems can achieve good network performance with very low CPU utilizations, and thus they can be expected to show a great improvement in overall performance. In experiments on a gigabit Ethernet network, although the embedded processor operated with a 300 MHz core clock, which was one-seventh the speed of the host CPUpsilas clock, the hybrid TOE showed a minimum latency of 17.4 mus and a maximum bandwidth of 736 Mbps. The RDMA mechanism exhibited a minimum latency of 20.6 mus and a maximum bandwidth of 642 Mbps. Most importantly, the hybrid TOE and the TOE-based RDMA mechanism gave CPU utilizations of less than 5.6% and 8.4%, respectively-approximately one-tenth the utilizations when TCP/IP and TCP/IP-based RDMA were processed by the host CPU.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125789593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Validation of executable application models mapped onto network-on-chip platforms 验证映射到片上网络平台上的可执行应用程序模型

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577689

Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, J. Nurmi, M. Glesner, F. Moraes

{"title":"Validation of executable application models mapped onto network-on-chip platforms","authors":"Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, J. Nurmi, M. Glesner, F. Moraes","doi":"10.1109/SIES.2008.4577689","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577689","url":null,"abstract":"Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124541990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Scalably distributed SystemC simulation for embedded applications 嵌入式应用的可扩展分布式SystemC仿真

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577715

Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, L. Thiele

引用次数: 49

Enabling self-reconfiguration on a video processing platform 在视频处理平台上启用自重构

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577676

K. F. Ackermann, Burghard Hoffmann, L. Indrusiak, M. Glesner

引用次数: 8

The effect of real-time software reuse in FPGAs and microcontrollers with respect to software faults fpga和微控制器中软件实时复用对软件故障的影响

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577692

F. Salewski, S. Kowalewski

引用次数: 1

TPR: Dead end aware table less position based routing scheme for low power data-centric wireless sensor networks

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577693

S. Madani, D. Weber, S. Mahlknecht

引用次数: 6

Services discovery and composition in Intelligent Environments for mobile devices 移动设备智能环境中的服务发现和组合

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577711

Reiner F. Perozzo, C. Pereira

{"title":"Services discovery and composition in Intelligent Environments for mobile devices","authors":"Reiner F. Perozzo, C. Pereira","doi":"10.1109/SIES.2008.4577711","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577711","url":null,"abstract":"Since the latest years, residential automation has been becoming a very discussed and recurrent subject. Part of such success is given by the meaningful diffusion and offer of portable electronic devices, with great power of computation, low energy consumption and, mainly, high level of connectivity. Joining the residential automation, the term ldquointelligent environmentsrdquo (IE) has been being defined, which brings a paradigm change, not considering the fact of just controlling devices, and leaving for a world where these are aware of everything that surrounds them. This paper proposes an architecture on management of services in IE for mobile devices, such as PDAs, cell phones and smart phones. The proposed architecture has three main characteristics: (i) discovery and remote composition of available services in the IE; (ii) adaptation of services and functionalities according to the userpsilas profile, using security policies with different levels of accessing the system; (iii) flexibility in the insertion of new residential automation devices, adding, dynamically, services to the IE. The architecture validation is presented through a case study which utilizes as scenery an automated seminaries room.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130352099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Infrastructure for web-based administration of embedded systems 用于基于web的嵌入式系统管理的基础设施

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577682

C. Hochberger, Christian Meusel

引用次数: 0

A digital receiver architecture for RFID readers RFID阅读器的数字接收器架构

2008 International Symposium on Industrial Embedded Systems Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577685

C. Angerer

{"title":"A digital receiver architecture for RFID readers","authors":"C. Angerer","doi":"10.1109/SIES.2008.4577685","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577685","url":null,"abstract":"This paper presents a digital receiver architecture for an RFID reader. The main challenge in RFID reader design is the detection of the backscattered signals from the tags, which can be severely complicated due to the largely varying scale of possible receive powers. Furthermore noise, which power depends on the environment can degrade the detection performance. The detection of the signals of the tags is additionally impeded by the very strong self interference at the reader with the carrier it needs to send in order to supply the tags with energy. To fight these various disturbances, a new RFID receiver algorithm is proposed, that sets its decision threshold adaptively, depending on the strength of the input signal, the noise power at the receiver and the extent of the carrier interference. This is the first algorithm for signal detection in RFID, setting its threshold accordingly to the environmental conditions, and thus leading to near optimum performance. Details of the implementation of the digital receiver architecture on an FPGA are introduced. Bit error ratio measurements have been carried out to rate the receivers performance, which have never been shown before for RFID receivers. Presented measurement results substantiate the performance of the suggested algorithm.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126755793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28