验证映射到片上网络平台上的可执行应用程序模型

Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, J. Nurmi, M. Glesner, F. Moraes
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引用次数: 14

摘要

由于当今嵌入式系统的设计尺寸、复杂性和异构性不断增加,设计人员需要新颖的设计方法来验证特定于应用程序的功能以及不同的平台实现方案。理想情况下,这应该发生在设计过程的早期阶段,这样设计师就可以在他们不得不提交特定的处理器架构或定制硬件实现之前探索设计空间。本文利用分层设计风格和面向参与者框架对异构计算模型(MoC)的支持,提出了一种多处理器嵌入式系统建模和验证的方法。所提出的方法是完全基于模型的,对应用程序和底层实现平台具有不同的建模风格。在本文中,我们重点关注使用托勒密II参与者和UML序列图建模的应用程序的验证,并将其映射到多处理器片上网络(NoC)平台上。我们还提供了一个案例研究,其中一个可执行应用程序模型被映射到不同的NoC拓扑,并显示了每个备选方案的通信延迟的仿真结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Validation of executable application models mapped onto network-on-chip platforms
Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.
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