2009 1st Asia Symposium on Quality Electronic Design最新文献

Next generation I/O power delivery design through SIPD co-analysis & comprehensive platform validation 通过SIPD联合分析和综合平台验证的下一代I/O电源交付设计

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-11-17 DOI: 10.1109/EPEPS.2009.5338441

Y. H. Tau, M. Chan

引用次数: 0

Statistical model for ring oscillator phase noise variability accounting for within-die process variation 考虑模具内工艺变化的环形振荡器相位噪声变异性统计模型

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206286

F. Khalek, H. Mostafa, M. Anis

{"title":"Statistical model for ring oscillator phase noise variability accounting for within-die process variation","authors":"F. Khalek, H. Mostafa, M. Anis","doi":"10.1109/ASQED.2009.5206286","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206286","url":null,"abstract":"Phase noise is one of the most restricted specifications in oscillators, especially ring oscillators. Phase noise will exhibit large fluctuations around its nominal value due to the increased process variation with technology scaling. These fluctuations will cause some fabricated ring oscillators not to meet the phase noise constraint and, hence, result in yield loss. This yield loss is expected to become worse especially for sub-90-nm technology nodes. In this paper, an analytical model for the phase noise variability in ring oscillators is proposed. The proposed model has been verified using Monte Carlo SPICE simulations for an industrial 65-nm CMOS technology and is found in good agreement. The model shows that for the commonly used differential-pair-based ring oscillators, the main contribution in phase noise variability comes from the differential pair tail transistor. It also shows that the phase noise variability is reduced as the supply voltage increases. These results can be used to mitigate the phase noise variability and improve the yield through proper sizing of the tail transistor or higher supply voltage.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117202208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Capacitive and inductive couplings in a distributed RLC interconnection line system: Additivity waveforms 分布式RLC互连线路系统中的容感性耦合:可加性波形

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206294

D. Deschacht, Y. Quéré

引用次数: 1

A CMOS radio frequency receiver for Bluetooth applications 用于蓝牙应用的CMOS射频接收器

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206241

Jenn-Tzer Yang, De-Wei Shen, P. Tsai, Ming-Jeui Wu

引用次数: 9

An analytic channel potential based model for dynamic depletion surrounding-gate mosfets with arbitrary doping level 基于解析通道电位的任意掺杂水平下动态耗尽环栅mosfet模型

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206285

Lining Zhang, Jian Zhang, Feng Liu, Lin Chen, Yiwen Xu, Wang Zhou, F. He

引用次数: 5

Comparative analysis of process variation impact on flip-flops soft error rate 工艺变化对触发器软错误率影响的对比分析

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206288

H. Mostafa, M. Anis, M. Elmasry

{"title":"Comparative analysis of process variation impact on flip-flops soft error rate","authors":"H. Mostafa, M. Anis, M. Elmasry","doi":"10.1109/ASQED.2009.5206288","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206288","url":null,"abstract":"Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitances and power supply voltages and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this paper for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop (SA-FF) is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop (SD-FF) exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed to guide flip-flops designers to select the best flip-flop topology that satisfies their specific circuit soft error rate constraints.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130625256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Area-effective programmable FSM-based MBIST for synchronous SRAM 基于区域有效可编程fsm的同步SRAM MBIST

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206271

Nurqamarina Binti Mohd Noor, A. Saparon, Yusrina Yusof, Mahmud Adnan

引用次数: 4

Analytical modeling of Hot Carrier Injection induced degradation in triple gate bulk FinFETs 热载流子注入诱发三栅极体finfet退化的分析建模

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206302

Nayereh Ghobadi, A. Afzali-Kusha, E. Asl-Soleimani

引用次数: 0

Novel low delay slew rate control I/Os 新颖的低延迟转换率控制I/ o

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206272

V. Narang, B. Arya, K. Rajagopal

引用次数: 7

Novel techniques for off-state current components reduction in double gate source-heterojunction-MOS-transistor 双栅极源-异质结- mos晶体管失态电流元件降低新技术

2009 1st Asia Symposium on Quality Electronic Design Pub Date : 2009-07-15 DOI: 10.1109/ASQED.2009.5206395

Mahsa Tahermaram, M. Vadizadeh, Hamdam Ghanatian, M. Fathipour

引用次数: 0