Novel low delay slew rate control I/Os

V. Narang, B. Arya, K. Rajagopal
{"title":"Novel low delay slew rate control I/Os","authors":"V. Narang, B. Arya, K. Rajagopal","doi":"10.1109/ASQED.2009.5206272","DOIUrl":null,"url":null,"abstract":"As technology is shrinking to sub 100nm, the sensitivity of circuits towards Process, Temperature, Voltage (PTV) and load variations is limiting circuit performance and yield [1–3]. For example in the specific case of IOs, it is difficult to meet various specifications like the rise and fall times, current drive strength, jitter, power and ground bounce across the wide range of I/O operating condition. Driver circuits are oversized to meet performance goals at slow corners. However, this leads to high current and Simultaneous Switching Noise (SSN) at fast corners. [1]. Further, high output edge switching rates lead to EMI issues [4]. In this paper, we propose a technique which can address the EMI and noise concerns without compromising the I/O performance. Our results show that the proposed scheme offers advantage over various PTV compensation schemes which do not target load compensation. The proposed scheme also offers advantage over the traditional slew rate control schemes which target PTV as well as load compensation but require a performance - noise tradeoff.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 1st Asia Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASQED.2009.5206272","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

As technology is shrinking to sub 100nm, the sensitivity of circuits towards Process, Temperature, Voltage (PTV) and load variations is limiting circuit performance and yield [1–3]. For example in the specific case of IOs, it is difficult to meet various specifications like the rise and fall times, current drive strength, jitter, power and ground bounce across the wide range of I/O operating condition. Driver circuits are oversized to meet performance goals at slow corners. However, this leads to high current and Simultaneous Switching Noise (SSN) at fast corners. [1]. Further, high output edge switching rates lead to EMI issues [4]. In this paper, we propose a technique which can address the EMI and noise concerns without compromising the I/O performance. Our results show that the proposed scheme offers advantage over various PTV compensation schemes which do not target load compensation. The proposed scheme also offers advantage over the traditional slew rate control schemes which target PTV as well as load compensation but require a performance - noise tradeoff.
新颖的低延迟转换率控制I/ o
随着技术缩小到100nm以下,电路对工艺、温度、电压(PTV)和负载变化的敏感性限制了电路的性能和产量[1-3]。例如,在IOs的具体情况下,很难满足各种规格,如上升和下降时间,电流驱动强度,抖动,功率和地反弹在大范围的I/O操作条件。驱动电路是超大的,以满足慢弯的性能目标。然而,这导致高电流和同时开关噪声(SSN)在快速弯道。[1]。此外,高输出边开关率导致EMI问题。在本文中,我们提出了一种可以在不影响I/O性能的情况下解决EMI和噪声问题的技术。结果表明,本文提出的方案优于各种不以负荷为目标的PTV补偿方案。该方案也比传统的摆率控制方案具有优势,传统的摆率控制方案以PTV和负载补偿为目标,但需要进行性能和噪声权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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