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IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.最新文献

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Compander systems with adaptive preemphasis/deemphasis using linear prediction 使用线性预测的自适应预强调/去强调的计算机系统
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579944
M. Holters, F. Keiler, U. Zolzer, J. Peissig
{"title":"Compander systems with adaptive preemphasis/deemphasis using linear prediction","authors":"M. Holters, F. Keiler, U. Zolzer, J. Peissig","doi":"10.1109/SIPS.2005.1579944","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579944","url":null,"abstract":"A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only for reduction, but also spectral shaping of noise induced e.g. in FM radio links. Evaluation using a simulation application shows a significant increase in perceived audio quality compared to conventional compander systems.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131321654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Distributed reconfigurable computing using XML Web services 使用XML Web服务的分布式可重构计算
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579939
D. Rodríguez, J.M. Sanchez, A. Duran
{"title":"Distributed reconfigurable computing using XML Web services","authors":"D. Rodríguez, J.M. Sanchez, A. Duran","doi":"10.1109/SIPS.2005.1579939","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579939","url":null,"abstract":"This paper describes an hybrid architecture based on XML Web services for remote executing of hardware applications. The architecture is based on a service provider that hosts a reconfigurable logic coprocessor. Reconfigurable logic can be used for accelerating complex algorithms as diverse as digital signal processing, cryptography, pattern matching or compressing and decompressing tasks. The hardware applications implemented in the coprocessor and the administration functions of the device are exposed to remote applications as XML Web services methods. These services can be accessed from the same server or from remote clients over intranet/Internet using standard Web protocols like HTTP, XML and SOAP; these clients execute remote tasks in non-homogeneous distributed reconfigurable systems. The proposed architecture has been implemented using Microsoft .Net Framework to develop the XML Web services and the RC1000-PP platform plus Handel-C from Celoxica to support the reconfigurable computing applications.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"6 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125287807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the importance of the excitation signal generation method in bandwidth extension of speech 论激励信号生成方法在语音带宽扩展中的重要性
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579907
S.A. Rodriguez, P. Burt
{"title":"On the importance of the excitation signal generation method in bandwidth extension of speech","authors":"S.A. Rodriguez, P. Burt","doi":"10.1109/SIPS.2005.1579907","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579907","url":null,"abstract":"The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtaining the excitation signal are analyzed and, based on this analysis, a new method is proposed. The influence of each method in the quality of the reconstructed wideband speech signal is evaluated by quantitative parameters of speech quality.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tiling parity-check matrix for reduced complexity high throughput low-density parity-check decoders 用于降低复杂度、高吞吐量、低密度校验解码器的平铺校验矩阵
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579964
A. Selvarathinam, G. Choi
{"title":"Tiling parity-check matrix for reduced complexity high throughput low-density parity-check decoders","authors":"A. Selvarathinam, G. Choi","doi":"10.1109/SIPS.2005.1579964","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579964","url":null,"abstract":"An approach for reducing hardware complexity of LDPC decoders is presented in this paper. Low-density parity-check (LDPC) codes have a sparse parity-check matrix (H matrix). In LDPC decoder, the H matrix is stored in memory and contains information about the parity check constraints. The approach presented in this paper constructs several sub-matrices (pseudo random patterns) that are repeatedly used to form the H matrix. The merits of this approach on the decoder architecture are two-fold. First, the switch logic associated with data forwarding in and out of the memory blocks, or alternately the routing of bit nodes to check nodes is simplified. Second, this approach reduces information stored in the design about the H matrix. Thus, the hardware complexity of the decoder is significantly reduced with an added advantage of increased throughput. LDPC code performance simulation results show that the proposed approach does not compromise the bit error rate performance (BER) compared to that of ideal/optimal H matrix for same code length (N = 2040) and rate.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114991631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Edge detection using quantitative combination of multiple operators 多算子定量组合边缘检测
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579893
S. Giannarou, T. Stathaki
{"title":"Edge detection using quantitative combination of multiple operators","authors":"S. Giannarou, T. Stathaki","doi":"10.1109/SIPS.2005.1579893","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579893","url":null,"abstract":"Although a number of diverse edge detection techniques can be found in many image processing publications, there is no single detection method that performs well in every possible image context. Information that could be missed by one detector may be captured by another. The purpose of this paper is to describe a new framework which allows us to quantitatively combine the methods of different edge detection operators in order to yield improved results for edge detection in an image. The so called receiver operating characteristics (ROC) analysis is employed in a novel fashion to form an optimum edge map that matches the outcomes of a preselected set of edge detectors. The results of applying the above ROC analysis technique are demonstrated and compared with individual edge detection methods.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125703595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Fast motion estimation by adaptive early termination 基于自适应早期终止的快速运动估计
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579951
E.A. Al Qaralleh, Tian-Sheuan Chang
{"title":"Fast motion estimation by adaptive early termination","authors":"E.A. Al Qaralleh, Tian-Sheuan Chang","doi":"10.1109/SIPS.2005.1579951","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579951","url":null,"abstract":"This paper presents a fast motion estimation (ME) algorithm by adaptively changing the early termination threshold for the current accumulated partial SAD value. The simulation results show that the proposed algorithm can provide the similar quality while save 77.9% and 50.6% of SAD computation when comparing with that in MPEG-4 VM 18.0 and H.264 JM9.0, respectively.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132022457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Mapping concurrent applications on network-on-chip platforms 在片上网络平台上映射并发应用程序
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579856
T. A. Bartic, D. Desmet, J. Mignolet, J. Miller, F. Robert
{"title":"Mapping concurrent applications on network-on-chip platforms","authors":"T. A. Bartic, D. Desmet, J. Mignolet, J. Miller, F. Robert","doi":"10.1109/SIPS.2005.1579856","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579856","url":null,"abstract":"Networks-on-chip have been proposed as the interconnect solution for building large systems-on-chip. Such platforms will be made of hardware cores, running concurrently to achieve high compute power and keep power consumption low. These platforms have many things in common with distributed systems. In this article we analyze the issues related to mapping concurrent applications on a networks-on-chip based platform. We show that the quality of the decisions made at different stages of mapping has a high impact on the overall system performance. The critical stages of application mapping for networks-on-chip platforms include partitioning the application into processing cores, mapping the communication between the cores, and resolving platform-dependent problems such as race conditions and multipoint-to-point communications. We investigate these problems using an MPEG4 video decoder application and we evaluate the performance of the mapped system in a simulation environment, using a SystemC networks-on-chip simulator.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114769181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A fast and accurate inverse discrete cosine transform 一个快速和准确的反离散余弦变换
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579844
A. Hinds, J.L. Mitchell
{"title":"A fast and accurate inverse discrete cosine transform","authors":"A. Hinds, J.L. Mitchell","doi":"10.1109/SIPS.2005.1579844","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579844","url":null,"abstract":"The discrete cosine transform (DCT) is a widely used transform in image and video processing applications. By its mathematical definition, it is a computationally complex algorithm defined by cosine multiplications to accomplish the transformation of data to and from the frequency domain. Consequently, the fast implementation of the DCT is an active area of research as engineers endeavor to mitigate its complexity by approximating it with fixed-point algorithms. This paper presents a new design methodology for the design of linear transforms; the application of which introduces an example fixed-point inverse DCT implementation that is both fast and accurate, and complies with the specification in the IEEE Std. 1180 - 1990 (currently withdrawn).","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134233354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture 低计算周期和高速递归DFT/IDFT: VLSI算法和体系结构
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579933
Lan-Da Van, Yuan-Chu Yu, Chun-Ming Huang, Chin-Teng Lin
{"title":"Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture","authors":"Lan-Da Van, Yuan-Chu Yu, Chun-Ming Huang, Chin-Teng Lin","doi":"10.1109/SIPS.2005.1579933","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579933","url":null,"abstract":"In this paper, we propose two low-computation cycle and high-speed recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architectures adopting the hybrid of Chebyshev polynomial and register-splitting scheme. The proposed core-type recursive architecture achieves half computation-cycle reduction as well as less critical period compared with the conventional second-order DFT/IDFT architecture. So as to further reduce the number of computation cycles, based on the new core-type design, we develop the folded-type recursive DFT/IDFT architecture with the same operating frequency. Moreover, from the derivation results, the operation of DFT and IDFT can be performed with the same structure under different configurations.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132435673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
2D phase-based matching in uncalibrated images 非校准图像中基于二维相位的匹配
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005. Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2005.1579887
Yi Xu, Jun Zhou, Guangtao Zhai
{"title":"2D phase-based matching in uncalibrated images","authors":"Yi Xu, Jun Zhou, Guangtao Zhai","doi":"10.1109/SIPS.2005.1579887","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579887","url":null,"abstract":"A novel 2D phase-based matching approach is proposed to resolve the general stereo image matching problem. It is different from the current uncalibrated matching techniques, most of which obtain 2D dense disparity map after the epipolar geometry has been recovered. In this paper, the disparity is directly estimated by simply establishing correspondences between quaternionic phase structures of two QWF (quaternion wavelet filtered) images. Real and short-length biorthogonal wavelet bases are exploited to build linear-phase quaternion wavelet filters (LPQWFs). Once phases are extracted from the QWF image pair, the disparity estimation is formed as a minimization process of a cost function, which is formulated as a similarity measure for comparing quaternion wavelet phases. With regard to the mismatches near phase singularities, phase stability constraints are imposed on cost aggregation stage. And multi-scale matching strategy is introduced to avoid phase wrapping problem and improve convergence speed. The experimental results are encouraging in various image pairs.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132450189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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