2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)最新文献_第2页

A new approach for adaptive failure diagnostics based on emulation test 一种基于仿真测试的自适应故障诊断方法

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457183

Steffen Ostendorff, H. Wuttke, Jörg Sachße, S. Köhler

引用次数: 10

Behavioral level dual-vth design for reduced leakage power with thermal awareness 行为级双v设计，减少泄漏功率与热意识

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457000

Junbo Yu, Qiang Zhou, G. Qu, Jinian Bian

{"title":"Behavioral level dual-vth design for reduced leakage power with thermal awareness","authors":"Junbo Yu, Qiang Zhou, G. Qu, Jinian Bian","doi":"10.1109/DATE.2010.5457000","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457000","url":null,"abstract":"Dual-Vth design is an effective leakage power reduction technique at behavioral synthesis level. It allows designers to replace modules on non-critical path with the high-Vth implementation. However, the existing constructive algorithms fail to find the optimal solution due to the complexity of the problem and do not consider the on-chip temperature variation. In this paper, we propose a two-stage thermal-dependent leakage power minimization algorithm by using dual-Vth library during behavioral synthesis. In the first stage, we quantitatively evaluate the timing impact on other modules caused by replacing certain modules with high Vth. Based on this analysis and the characteristics of the dual-Vth module library, we generate a small set of candidate solutions for the module replacement. Then in the second stage, we obtain the on-chip thermal information from thermal-aware floorplanning and thermal analysis to select the final solution from the candidate set. Experimental results show an average of 17.8% saving in leakage power consumption and a slightly shorter runtime compared to the best known work. In most cases, our algorithm can actually find the optimal solutions obtained from a complete solution space exploration.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116329311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

SigNet: Network-on-chip filtering for coarse vector directories SigNet:用于粗矢量目录的片上网络过滤

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457028

Natalie D. Enright Jerger

引用次数: 7

Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity 准线性复杂度混合信号集成电路的可变性感知可靠性仿真

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456972

Elie Maricau, G. Gielen

引用次数: 18

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits 采用亚阈值源耦合电路的超低功耗混合信号设计平台

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457110

A. Tajalli, Y. Leblebici

引用次数: 11

Layout-aware pseudo-functional testing for critical paths considering power supply noise effects 考虑电源噪声影响的关键路径布局感知伪功能测试

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457037

Xiao Liu, Yubin Zhang, F. Yuan, Q. Xu

引用次数: 13

Memory testing with a RISC microcontroller 用RISC微控制器进行内存测试

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457210

A. V. Goor, G. Gaydadjiev, S. Hamdioui

引用次数: 31

Cool MPSoC programming 酷酷的MPSoC编程

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457047

R. Leupers, L. Thiele, Xiaoning Nie, B. Kienhuis, Matthias Weiss, T. Isshiki

{"title":"Cool MPSoC programming","authors":"R. Leupers, L. Thiele, Xiaoning Nie, B. Kienhuis, Matthias Weiss, T. Isshiki","doi":"10.1109/DATE.2010.5457047","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457047","url":null,"abstract":"This paper summarizes a special session on multi-core/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key drivers for MPSoC platform evolution. Heterogeneous multi-processor architectures achieve high performance and can lead to a significant reduction in energy consumption for this class of applications. However, just designing energy efficient hardware is not enough. Programming models and tools for efficient MPSoC programming are equally important to ensure optimum platform utilization. Unfortunately, this discipline is still in its infancy, which endangers the return on investment for MPSoC architecture designs. On one hand there is a need for maintaining and gradually porting a large amount of legacy code to MPSoCs. On the other hand, special C language extensions for parallel programming as well as adapted process network programming models provide a great opportunity to completely rethink the traditional sequential programming paradigm for sake of higher efficiency and productivity. MPSoC programming is more than just code parallelisation, though. Besides energy efficiency, limited and specialized processing resources, and real-time constraints also growing software complexity and mapping of simultaneous applications need to be taken into account. We analyze the programming methodology requirements for heterogeneous MPSoC platforms and outline new approaches.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Ultra-high throughput string matching for Deep Packet Inspection 用于深度包检测的超高吞吐量字符串匹配

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457172

A. Kennedy, Xiaojun Wang, Z. Liu, B. Liu

{"title":"Ultra-high throughput string matching for Deep Packet Inspection","authors":"A. Kennedy, Xiaojun Wang, Z. Liu, B. Liu","doi":"10.1109/DATE.2010.5457172","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457172","url":null,"abstract":"Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing number of attacks which must be searched for has meant hardware acceleration has become essential in the prevention of DPI becoming a bottleneck to a network if used on an edge or core router. In this paper we present a new multi-pattern matching algorithm which can search for the fixed strings contained within these rules at a guaranteed rate of one character per cycle independent of the number of strings or their length. Our algorithm is based on the Aho-Corasick string matching algorithm with our modifications resulting in a memory reduction of over 98% on the strings tested from the Snort ruleset. This allows the search structures needed for matching thousands of strings to be small enough to fit in the on-chip memory of an FPGA. Combined with a simple architecture for hardware, this leads to high throughput and low power consumption. Our hardware implementation uses multiple string matching engines working in parallel to search through packets. It can achieve a throughput of over 40 Gbps (OC-768) when implemented on a Stratix 3 FPGA and over 10 Gbps (OC-192) when implemented on the lower power Cyclone 3 FPGA.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117320501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Intent-leveraged optimization of analog circuits via homotopy 基于同伦的模拟电路意图杠杆优化

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457068

M. Jeeradit, Jaeha Kim, M. Horowitz

引用次数: 1