E. Tsunashima, A. Okuno, K. Nagai, M. Kadowaki, E. Akiyama
{"title":"A multilayer surface mount technology elevated by an aramid-paper and epoxy-resin composite","authors":"E. Tsunashima, A. Okuno, K. Nagai, M. Kadowaki, E. Akiyama","doi":"10.1109/EMTS.1989.68991","DOIUrl":"https://doi.org/10.1109/EMTS.1989.68991","url":null,"abstract":"Experimental results are presented on an innovative SMT (surface mount technology) aramid-paper/epoxy matrix structure. An investigation of the interlayer adhesion of this composite to copper foils shows that a moderate adhesion force has been kept through the heat aging process without cupric oxide treatment on the foils. Hole piercing by a one-shot punching method and the implementation of printed polymer resistors with improved performance are demonstrated.<<ETX>>","PeriodicalId":432803,"journal":{"name":"Proceedings. Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium,","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121872593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Preparation of custom gate array silicon wafers to handle specific wafer size in metallization process","authors":"F. Ghahghahi, P. Hoss","doi":"10.1109/EMTS.1989.69001","DOIUrl":"https://doi.org/10.1109/EMTS.1989.69001","url":null,"abstract":"A wafer reduction sizing and backgrinding process has been developed to downsize larger wafers received from semiconductor vendors to 4-in. diameter and personalize them through Tandem's prototype wafer Fab line. This process avoided the equipment changes necessary to convert to a 5- or 6-in. wafer line, yet made it possible to accept larger wafers from vendors. The wafer sizing and backside grinding processes have been in place at Tandem for two years at a yield of 98%. Process steps are described in detail.<<ETX>>","PeriodicalId":432803,"journal":{"name":"Proceedings. Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium,","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133671141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low stress silver-glass die attach material","authors":"M. Nguyen","doi":"10.1109/EMTS.1989.68979","DOIUrl":"https://doi.org/10.1109/EMTS.1989.68979","url":null,"abstract":"The sintering characteristics of a silver-filled lead borate glass composite were studied since it influences die stresses. This is especially true for very-large-area die attachments. The kinetics of silver particle sintering in the presence of liquid-phase glass was examined by dilatometry and electron microscopy. During heat treatment, the sintering rate is significantly increased after the glass becomes liquid. This can cause excessive die stresses, resulting in cracks, typically at the die-bond interface, and/or poor adhesion. The sintering process is influenced by material parameters such as silver flake surface area, glass transition temperature, and additives, and by process profiles such as temperature ramp rate and dwell time. It was found that, by adding a small amount of appropriate additives, it is possible to either increase or decrease the sintering rate significantly. Thus, stress relief in large-area dice can be achieved by using additives in silver-glass to control the sintering rate.<<ETX>>","PeriodicalId":432803,"journal":{"name":"Proceedings. Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium,","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116467073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analyzing the mechanical strength of SMT attached solder joints","authors":"W. Chen","doi":"10.1109/EMTS.1989.68952","DOIUrl":"https://doi.org/10.1109/EMTS.1989.68952","url":null,"abstract":"Analytic approaches to the pull strength and shear strength of SMT (surface mount technology) attached solder joints have been studied by mathematical models. The predicted pull/shear strength of leaded ceramic quad packages correlated with the experimentally measured data quite well. Lead/pad design is shown to have the most significant impact on the solder joint strength. The design rules for butt leaded and land patterns have been developed. The predictive models have been used for defining the design guidelines for selecting the optimum lead/pad configurations, the minimum solder volume, and the maximum component misalignment for fine pitch SMT assemblies. The SPC (statistical process control) limits established through destructive mechanical testing can be used as online monitors for checking the short-term reliability of solder joints. The short-term reliability data generated by conducting destructive mechanical testing are complementary to the long-term reliability test.<<ETX>>","PeriodicalId":432803,"journal":{"name":"Proceedings. Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium,","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115143974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Bogatin, P. Ghandi, G. Weihe, S. Szeto, C. Lofdahl
{"title":"Enhanced high speed performance from HDI thin film multi-chip modules","authors":"E. Bogatin, P. Ghandi, G. Weihe, S. Szeto, C. Lofdahl","doi":"10.1109/EMTS.1989.69003","DOIUrl":"https://doi.org/10.1109/EMTS.1989.69003","url":null,"abstract":"A novel packaging technology, ideal for CMOS multichip modules, is described. Thin-film metal and polymer dielectric are used to fabricate five metal-layer structures with 25- mu m-wide traces and 11- mu m-thick dielectric layers. Features on the top pad layer can be fabricated to match the chip pads, allowing for orthogonal wire bonding with no fanout. In a microstrip configuration, the typical capacitance is 3.5 pF/in with a time of flight of about 160 ps/in. The propagation velocity (or phase velocity) for a sinusoidal wave is about 54% of the speed of light in vacuum. Multichip modules have been fabricated for applications ranging from two to 35 ICs, plus associated capacitors and resistors. With these features, the interconnect related propagation delay due to the capacitive loading or time of flight is in most cases less than the switching time of the driver gates (normally 1 ns). Low inductance power and ground planes are used throughout the module with on-board decoupling capacitors. Wire bonds on a 6-mil substrate pitch can be made routinely. The 6-mil pitch consists of a 4-mil pad and a 2-mil spacing between pads. With this pitch and short conductor lengths, bonding parasitics less than 1.2 nH are possible. Simultaneous switching noise is drastically reduced over conventional single-chip packaging methods.<<ETX>>","PeriodicalId":432803,"journal":{"name":"Proceedings. Seventh IEEE/CHMT International Electronic Manufacturing Technology Symposium,","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125127830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}