Preparation of custom gate array silicon wafers to handle specific wafer size in metallization process

Abstract

A wafer reduction sizing and backgrinding process has been developed to downsize larger wafers received from semiconductor vendors to 4-in. diameter and personalize them through Tandem's prototype wafer Fab line. This process avoided the equipment changes necessary to convert to a 5- or 6-in. wafer line, yet made it possible to accept larger wafers from vendors. The wafer sizing and backside grinding processes have been in place at Tandem for two years at a yield of 98%. Process steps are described in detail.<>