Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware最新文献

Scalability problems of digital circuit evolution evolvability and efficient designs 数字电路演化的可扩展性问题，演化与高效设计

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869342

Vesselin K. Vassilev, J. Miller

{"title":"Scalability problems of digital circuit evolution evolvability and efficient designs","authors":"Vesselin K. Vassilev, J. Miller","doi":"10.1109/EH.2000.869342","DOIUrl":"https://doi.org/10.1109/EH.2000.869342","url":null,"abstract":"A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit. This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster, since the building blocks of the circuit are sub-circuits rather than two-input gates. This can also be a disadvantage, since the number of gates of the evolved designs grows as the size of the modules used.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126635632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 119

Kernel-based pattern recognition hardware: its design methodology using evolved truth tables 基于核的模式识别硬件:使用进化真值表的设计方法

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869363

M. Yasunaga, Taro Nakamura, J. H. Kim, I. Yoshihara

引用次数: 3

The test vector problem and limitations to evolving digital circuits 测试矢量问题和发展中的数字电路的限制

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869344

Kosuke Imamura, J. Foster, A. Krings

引用次数: 31

Self-repairable EPLDs: design, self-repair, and evaluation methodology 可自我修复的epld:设计、自我修复和评估方法

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869356

Chong H. Lee, M. Perkowski, D. Hall, David S. Jun

引用次数: 4

Safe intrinsic evolution of Virtex devices Virtex设备的安全内在进化

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869357

G. Hollingworth, Steve Smith, A. Tyrrell

引用次数: 55

Evolutionary design of single electron systems 单电子系统的进化设计

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869348

A. Thompson, C. Wasshuber

引用次数: 9

A reconfigurable platform for the automatic synthesis of analog circuits 用于模拟电路自动合成的可重构平台

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869346

R. Zebulum, C. C. Santini, H. T. Sinohara, M. Pacheco, M. Vellasco, M. H. Szwarcman

{"title":"A reconfigurable platform for the automatic synthesis of analog circuits","authors":"R. Zebulum, C. C. Santini, H. T. Sinohara, M. Pacheco, M. Vellasco, M. H. Szwarcman","doi":"10.1109/EH.2000.869346","DOIUrl":"https://doi.org/10.1109/EH.2000.869346","url":null,"abstract":"Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and Field Programmable Analog Arrays (FPAAs) constitute the state of the art in the technology of reconfigurable chips, referring to digital and analog devices respectively. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. These are essential features for systems that need to perform for a long time in harsh environments such as those employed in space exploration missions. Automatic reconfiguration of field programmable devices may potentially be driven by Evolutionary Computation techniques such as Generic Algorithms. FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. In this article we propose a new model of reconfigurable analog circuit and describe its application in the intrinsic evolution of a simple logic inverter.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126575372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Evolutionary multiobjective design of combinational logic circuits 组合逻辑电路的进化多目标设计

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869354

C. C. Coello, A. H. Aguirre, B. Buckles

引用次数: 67

Toward self-repairing and self-replicating hardware: the Embryonics approach 走向自我修复和自我复制的硬件:胚胎学方法

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869358

D. Mange, M. Sipper, A. Stauffer, G. Tempesti

{"title":"Toward self-repairing and self-replicating hardware: the Embryonics approach","authors":"D. Mange, M. Sipper, A. Stauffer, G. Tempesti","doi":"10.1109/EH.2000.869358","DOIUrl":"https://doi.org/10.1109/EH.2000.869358","url":null,"abstract":"The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the design of highly robust integrated circuits, endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. The Embryonics architecture is based on four hierarchical levels of organization: 1) The basic primitive of our system is the molecule, a multiplexer-based element of a novel programmable circuit. 2) A finite set of molecules makes up a cell, essentially a small processor with an associated memory. 3) A finite set of cells makes up an organism, an application-specific multiprocessor system. 4) The organism can itself replicate, giving rise to a population of identical organisms. In the conclusion, we describe our ongoing research efforts to meet three challenges: a scientific challenge, that of implementing the original specifications formulated by John von Neumann; a technical challenge, that of realizing very robust integrated circuits; and a biological challenge, that of attempting to show that the genomes of artificial and natural organisms share common properties.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126191102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

Behaviour of a building block for intrinsic evolution of analogue signal shaping and filtering circuits 模拟信号整形和滤波电路固有演化的构建模块的行为

Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware Pub Date : 2000-07-13 DOI: 10.1109/EH.2000.869349

S. J. Flockton, K. Sheehan

引用次数: 3