2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)最新文献_第2页

Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography 介入计算机断层扫描中数据采集的可配置流水线数据路径

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00044

Daniele Passaretti, Thilo Pionteck

引用次数: 2

Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices 使用hls4ml在互连的FPGA设备上映射卷积神经网络

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00062

Evangelos Mageiropoulos, Nikolaos Chrysos, Nikolaos Dimou, M. Katevenis

引用次数: 1

AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design AutoTEA:用于GRM FPGA设计的晶体管级高效精确的自动优化

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00043

Yanze Li, Yufan Zhang, Jiafeng Liu, Jian Wang, Jinmei Lai, G. Qu

引用次数: 1

FPGA-accelerated Iterative Reconstruction for Transmission Electron Tomography 透射电子断层扫描的fpga加速迭代重建

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00025

Linjun Qiao, Guojie Luo, Wentai Zhang, M. Jiang

{"title":"FPGA-accelerated Iterative Reconstruction for Transmission Electron Tomography","authors":"Linjun Qiao, Guojie Luo, Wentai Zhang, M. Jiang","doi":"10.1109/FCCM51124.2021.00025","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00025","url":null,"abstract":"Transmission electron tomography (TET) is a widely used biomedical imaging technique. Iterative reconstruction with regularization is the common approach to obtain high-quality reconstructed images for TET. Mumford-Shah (MS) regularization has the advantage in preserving image edges; but it is computation and memory-intensive because it is NP-hard when applied to TET. In this work, we design an FPGA accelerator for iterative image reconstruction for TET with the MS regularization. We first design the accelerator with multiple processing elements (PE) to leverage the parallelism in the TET reconstruction. We then schedule the forward projection and back projection according to the imaging geometry of TET to optimize off-chip memory access. Finally, we optimize the local buffer with customized partitioning for the stencil memory access of basic operations to increase the throughput of a single PE. Our FPGA accelerator achieves 6.68X and 1.87X speedup with the same image quality compared with the same algorithm implemented on CPU and GPU, respectively. And the off-chip bandwidth requirements of forward and back projection are reduced by one to two orders of magnitude. Compared with the state-of-the-art acceleration works on GPU and FPGA, we achieve 1.18X and 1.91X throughput, respectively.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131771020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Pharos: a Performance Monitor for Multi-FPGA Systems Pharos:多fpga系统的性能监视器

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00056

Arzhang Rafii, P. Chow, Welson Sun

引用次数: 0

A Tunable Dual-Edge Time-to-Digital Converter 一种可调谐的双边缘时间-数字转换器

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00040

Colin Drewes, S. Harris, Winnie Wang, Richard Appen, Olivia Weng, R. Kastner, William Hunter, Christopher McCarty, D. Richmond

引用次数: 0

The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable Hardware X-Drop的重要性:可重构硬件上的高性能基因组比对

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00023

Alberto Zeni, Guido Walter Di Donato, Lorenzo Di Tucci, Marco Rabozzi, M. Santambrogio

{"title":"The Importance of Being X-Drop: High Performance Genome Alignment on Reconfigurable Hardware","authors":"Alberto Zeni, Guido Walter Di Donato, Lorenzo Di Tucci, Marco Rabozzi, M. Santambrogio","doi":"10.1109/FCCM51124.2021.00023","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00023","url":null,"abstract":"Pairwise sequence alignment accounts for the majority of key genome analysis applications’ runtime. Because of the quadratic time complexity of exact alignment algorithms, the community is moving away from exact algorithms in favor of heuristics that only compute high-quality results. However, the state of the art lacks hardware-accelerated versions of these heuristic algorithms as the vast majority of the available solutions still rely on implementing exact alignment algorithms. Moreover, hardware-based implementations lack high-level APIs that can simplify their integration in commonly used genomic pipelines, hindering their applicability in real-world scenarios. In this context, we present the first high-performance FPGA implementation of the popular X-drop heuristic alignment algorithm and provide an easy-to-use API for its integration. On a Xilinx Alveo U280, our FPGA design achieves up to 5× speed-up over SeqAn, the state-of-the-art software version of the algorithm, running on two Intel Xeon processors using 80 CPU threads. Moreover, our design is also 3.45× faster than ksw2, a state-of-the-art vectorized alignment algorithm that performs a similar heuristic to the one employed in the X-drop algorithm. Finally, our implementation also outperforms LOGAN, a recently published GPU implementation of X-drop running on an Nvidia Tesla V100, by a factor of 1.5×.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127486810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

FFIVE: An FPGA Framework for Interactive VNF Environments 交互式VNF环境的FPGA框架

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00050

Juan Camilo Vega, M. Ewais, A. Leon-Garcia, P. Chow

引用次数: 0

ARC: Reconfigurable Cache Security Assurance with Application-Specific Randomized Mapping in FPGA-Based Heterogeneous Computing 基于fpga的异构计算中应用特定随机映射的可重构缓存安全保证

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00042

Sanjay Gandham, Rakin Muhammad Shadab, Mingjie Lin

{"title":"ARC: Reconfigurable Cache Security Assurance with Application-Specific Randomized Mapping in FPGA-Based Heterogeneous Computing","authors":"Sanjay Gandham, Rakin Muhammad Shadab, Mingjie Lin","doi":"10.1109/FCCM51124.2021.00042","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00042","url":null,"abstract":"Modem general purpose processors suffer from cache side-channel attacks (SCA) such as Prime+Probe [1] where the attacker can infer the victim’s information. Last-Level caches(LLC) are particularly vulnerable as they are shared between different cores of the processor. Encryption-based randomized caches such as CEASER [2] have been successful in mitigating conflict-based SCA by stopping the attackers from creating eviction sets but they have a few drawbacks 1) Encryption and remapping is done at all times, even when not performing security-critical tasks and 2) These mitigation techniques provide no defense against flush- based cache attacks such as Flush+Reload. Moreover, such randomized caches employing least-recently used (LRU) replacement policy incur impractical overheads to provide defense against conflict-based SCA. On the other hand, randomized caches employing random replacement policy can mitigate theses attacks with relatively low overhead but suffer from lower hit rate due to inefficient replacement policy. In this paper we show that moving the shared LLC of the processor to the programmable fabric of heterogeneous devices such as FPGA+CPU system-on-chips provides high degree of flexibility in terms of security and performance. To this end, we propose two randomized cache modes 1) Fast: Generic cache using LRU policy while providing no security against SCA and 2) Secure: Randomized cache using random replacement policy that can mitigate SCA. When the LLC is implemented on the reprogrammable fabric of the FPGA, modern FPGA+CPU SoCs ability to reconfigure the FPGA fabric during run-time allows the cache to switch between these two modes. Additionally, we propose a novel randomized cache mechanism, ARC, that can mitigate not only conflict-based attacks but also flush- based cache attacks.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115235701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAs 在fpga上测试Optane DC持久内存模块

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00019

Jialiang Zhang, Nicholas Beckwith, J. Li

{"title":"GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAs","authors":"Jialiang Zhang, Nicholas Beckwith, J. Li","doi":"10.1109/FCCM51124.2021.00019","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00019","url":null,"abstract":"Scalable nonvolatile memory DIMMs become commercially available on FPGAs with the release of Intel’s Optane DC Persistent Memory (DCPM) product. This new class of memory combines the benefits of DRAM-like solid-state memory (fast, byte addressable) and Flash-like persistent storage (cost- effective, non-volatile), making FPGA highly competitive in accelerating large-scale machine learning and data analytics applications. Despite of the great promise, the performance characteristics of Optane DCPM remains relatively alien to FPGA developers compared to conventional DDRx DRAM or SSD. Recent preliminary studies all use CPU-based systems running full OS stack that limits their ability to characterize the detailed performance characteristics of the Optane DCPM. To fully exploit the advantages of Optane DCPM in FPGA-based accelerator design, we present the first FPGA-based Optane DCPM profiling framework, named GORDON 1 on Stratix 10 DX FPGA. By leveraging the flexibility of the FPGA in building custom logic and the FPGA-specific features for Optane DCPM, GORDON addresses the fundamental limitations of prior CPU- based profiling. The detailed understanding on Optane DCPM may also benefit system design and optimization beyond FPGAs using CPUs and GPUs.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125486276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2