2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)最新文献

Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs 多租户fpga中多功能张量加速器的远程电源攻击

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00037

Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, R. Tessier, Jakub Szefer

{"title":"Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs","authors":"Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, R. Tessier, Jakub Szefer","doi":"10.1109/FCCM51124.2021.00037","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00037","url":null,"abstract":"Architectural details of machine learning models are crucial pieces of intellectual property in many applications. Revealing the structure or types of layers in a model can result in a leak of confidential or proprietary information. This issue becomes especially concerning when the machine learning models are executed on accelerators in multi-tenant FPGAs where attackers can easily co-locate sensing circuitry next to the victim’s machine learning accelerator. To evaluate such threats, we present the first remote power attack that can extract details of machine learning models executed on an off-the-shelf domain-specific instruction set architecture (ISA) based neural network accelerator implemented in an FPGA. By leveraging a time-to-digital converter (TDC), an attacker can deduce the composition of instruction groups executing on the victim accelerator, and recover parameters of General Matrix Multiplication (GEMM) instructions within a group, all without requiring physical access to the FPGA. With this information, an attacker can then reverse-engineer the structure and layers of machine learning models executing on the accelerator, leading to potential theft of proprietary information.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127478788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

TOCO: A Systolic Network for Efficient Transposed Convolutions with Output-Reuse Paths 具有输出复用路径的高效转置卷积的收缩网络

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00060

Zhengzheng Ma, Guojie Luo

引用次数: 0

Reconfigurable Synthesizable Synchronization FIFOs 可重构的可合成同步fifo

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00057

Ameer Abdelhadi, He Li

引用次数: 0

Trusted Configuration in Cloud FPGAs 云fpga中的可信配置

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00036

Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, A. Sadeghi, N. Mentens

{"title":"Trusted Configuration in Cloud FPGAs","authors":"Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, A. Sadeghi, N. Mentens","doi":"10.1109/FCCM51124.2021.00036","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00036","url":null,"abstract":"In this paper we tackle the open paradoxical challenge of FPGA-accelerated cloud computing: On one hand, clients aim to secure their Intellectual Property (IP) by encrypting their configuration bitstreams prior to uploading them to the cloud. On the other hand, cloud service providers disallow the use of encrypted bitstreams to mitigate rogue configurations from damaging or disabling the FPGA. Instead, cloud providers require a verifiable check on the hardware design that is intended to run on a cloud FPGA at the netlist-level before generating the bitstream and loading it onto the FPGA, therefore, contradicting the IP protection requirement of clients. Currently, there exist no practical solution that can adequately address this challenge.We present the first practical solution that, under reasonable trust assumptions, satisfies the IP protection requirement of the client and provides a bitstream sanity check to the cloud provider. Our proof-of-concept implementation uses existing tools and commodity hardware. It is based on a trusted FPGA shell that utilizes less than 1% of the FPGA resources on a Xilinx VCU118 evaluation board, and an Intel SGX machine running the design checks on the client bitstream.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130271780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design 用高级描述语言扩展HLS用于可配置算法级空间结构设计

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00048

Chengyue Wang, Sitao Huang, Wen-mei W. Hwu, Deming Chen

引用次数: 0

HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection HEDAcc:基于fpga的高阶上位检测加速器

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00022

Gaspar Ribeiro, Nuno Neves, Sergio Santander-Jiménez, A. Ilic

{"title":"HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection","authors":"Gaspar Ribeiro, Nuno Neves, Sergio Santander-Jiménez, A. Ilic","doi":"10.1109/FCCM51124.2021.00022","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00022","url":null,"abstract":"The manifestation of important genetic diseases is often a consequence of the interactions between Single Nucleotide Polymorphisms (SNPs), also known as epistasis. Detecting epistasis for high-order interactions results in a huge computational complexity, as the number of SNP combinations to be evaluated exponentially grows with the interaction order. To address this challenge, state-of-the-art exhaustive search-based methods for epistasis detection rely on GPUs and FPGAs to provide high-performance solutions tailored for a specific order (second and rarely third-order interactions) and/or specific data-set sizes. In this paper, a novel parameterizable architecture is proposed that enables the deployment of FPGA-based accelerators targeting any order of interactions and any data-set size. By relying on a set of algorithmic and architecture optimizations, the proposed accelerator showed to outperform current FPGA accelerators for second and third-order interactions by as much as 4.6× and 9.5×, respectively. The proposed solution also showed comparable performance to current GPGPU third-order implementations, while consuming up to 8.2× less energy. Finally, the proposed architecture allowed for the implementation of a fourth-order epistasis detection accelerator in an FPGA platform.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"12 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129959714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA ESCA:在UltraScale+ FPGA上具有数据级并行性的基于事件的Split-CNN架构

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00028

Pankaj Bhowmik, Jubaer Hossain Pantho, Joel Mandebi Mbongue, C. Bobda

引用次数: 6

Accelerating Large-Scale Nearest Neighbor Search with Computational Storage Device 利用计算存储设备加速大规模最近邻搜索

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00041

Ji-Hoon Kim, Y. Park, Jaeyoung Do, S. Ji, Joo-Young Kim

引用次数: 2

HLS-Compatible, Embedded-Processor Stream Links hls兼容，嵌入式处理器流链接

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00033

Eric Micallef, Yuanlong Xiao, A. DeHon

引用次数: 0

DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers DMA美杜莎:400 Gbps DMA传输的基于fpga的独立厂商架构

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-05-01 DOI: 10.1109/FCCM51124.2021.00045

J. Kubálek, Jakub Cabal, Martin Spinler, R. Iša

引用次数: 3