2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)最新文献_第6页

Enabling OpenMP Task Parallelism on Multi-FPGAs 在多fpga上启用OpenMP任务并行

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-03-19 DOI: 10.1109/FCCM51124.2021.00047

Ramon Nepomuceno, Renan Sterle, G. Valarini, M. Pereira, H. Yviquel, G. Araújo

引用次数: 2

Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design 基于内存和计算优化的FPGA设计求解大Top-K图特征问题

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-03-18 DOI: 10.1109/FCCM51124.2021.00017

Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, M. Santambrogio

引用次数: 4

unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation unzipFPGA:增强基于fpga的CNN引擎的动态权重生成

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-03-09 DOI: 10.1109/FCCM51124.2021.00027

Stylianos I. Venieris, J. Fernández-Marqués, N. Lane

{"title":"unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation","authors":"Stylianos I. Venieris, J. Fernández-Marqués, N. Lane","doi":"10.1109/FCCM51124.2021.00027","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00027","url":null,"abstract":"Single computation engines have become a popular design choice for FPGA-based convolutional neural networks (CNNs) enabling the deployment of diverse models without fabric reconfiguration. This flexibility, however, often comes with significantly reduced performance on memory-bound layers and resource underutilisation due to suboptimal mapping of certain layers on the engine’s fixed configuration. In this work, we investigate the implications in terms of CNN engine design for a class of models that introduce a pre-convolution stage to decompress the weights at run time. We refer to these approaches as on-the-fly. To minimise the negative impact of limited bandwidth on memory-bound layers, we present a novel hardware component that enables the on-chip on-the-fly generation of weights. We further introduce an input selective processing element (PE) design that balances the load between PEs on suboptimally mapped layers. Finally, we present unzipFPGA, a framework to train on-the-fly models and traverse the design space to select the highest performing CNN engine configuration. Quantitative evaluation shows that unzipFPGA yields an average speedup of 2.14× and 71% over optimised status-quo and pruned CNN engines under constrained bandwidth and up to 3.69× higher performance density over the state-of-the-art FPGA-based CNN accelerators.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs 时钟:fpga上多速率图像处理应用的资源高效静态调度

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-02-17 DOI: 10.1109/FCCM51124.2021.00030

Dillon Huff, Steve Dai, P. Hanrahan

{"title":"Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs","authors":"Dillon Huff, Steve Dai, P. Hanrahan","doi":"10.1109/FCCM51124.2021.00030","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00030","url":null,"abstract":"Image processing applications can benefit tremendously from FPGA acceleration. However, hardware accelerators for these applications look very different from the programs that image processing algorithm designers are accustomed to writing. As a result, many image processing hardware compilers have been designed to generate hardware accelerators from high-level specifications of image processing algorithms. Unfortunately, all of these compilers either exclude crucial access patterns, do not scale to realistic size applications, or rely on a compilation process in which each stage of the application is an independently scheduled module that sends data to its consumers through FIFOs which adds resource and energy overhead while inhibiting synthesis optimizations.In this paper we present a new algorithm for compiling image processing applications, Clockwork, that uses a combination of techniques from polyhedral analysis and synchronous dataflow (SDF) to overcome these limitations. Clockwork compiles the entire application into one flat, statically scheduled module. As a result, accelerators produced by Clockwork have fixed latency, cannot deadlock, and have no resource overhead from inter-stage FIFOs. We show that designs generated by Clockwork achieve on average a 55% reduction in LUTs, a 30% reduction in flip-flops, and a 22% reduction in BRAMs compared to a state-of-the-art stencil compiler at the same throughput, while handling a wider range of access patterns. Clockwork scales to applications with more than 100,000 LUTs. For an application with dozens of stages, Clockwork achieves energy efficiency 260x that of an 8 thread Intel CPU, 17x that of an NVIDIA K80 GPU, and 2.4x that of an NVIDIA V100 GPU.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126265258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

BoostGCN: A Framework for Optimizing GCN Inference on FPGA 基于FPGA的GCN推理优化框架

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2021-02-17 DOI: 10.1109/FCCM51124.2021.00012

Bingyi Zhang, R. Kannan, V. Prasanna

{"title":"BoostGCN: A Framework for Optimizing GCN Inference on FPGA","authors":"Bingyi Zhang, R. Kannan, V. Prasanna","doi":"10.1109/FCCM51124.2021.00012","DOIUrl":"https://doi.org/10.1109/FCCM51124.2021.00012","url":null,"abstract":"Graph convolutional networks (GCNs) have revolutionized many big data applications, such as recommendation systems, traffic prediction, etc. However, accelerating GCN inference is challenging due to (1) massive external memory traffic and irregular memory access, (2) workload imbalance due to skewed degree distribution, and (3) intra-stage load imbalance caused by two heterogeneous computation phases of the algorithm. To address the above challenges, we propose a framework named BoostGCN to optimize GCN inference on FPGA. First, we develop a novel hardware-aware Partition-Centric Feature Aggregation (PCFA) scheme that leverages 3-D partitioning with the vertex-centric computing paradigm. This increases on-chip data reuse and reduces the total data communication volume with external memory. Second, we design a novel hardware architecture to enable pipelined execution of the two heterogeneous computation phases. We develop a low-overhead task scheduling strategy to reduce the pipeline stalls caused by the two computation phases. Third, we provide a complete GCN acceleration framework on FPGA with optimized RTL templates. It can generate hardware designs based on the customized configuration and is adaptable to various GCN models. Using our framework, we generate accelerators for various GCN models on a state-of-the-art FPGA platform and evaluate our designs using widely used datasets. Experimental results show that the accelerators produced by our framework achieve significant speedup compared with state-of-the-art implementations on CPU (≈ 100×), GPU (≈ 30×), prior FPGA accelerator (3-45)×.","PeriodicalId":430997,"journal":{"name":"2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122528959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

[Title page iii] [标题页iii]

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2018-06-01 DOI: 10.1109/WETICE.2009.2

Mikkilineni

引用次数: 0

Subreviewers Subreviewers

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 1900-01-01 DOI: 10.1109/fccm51124.2021.00008

引用次数: 0

[Copyright notice] (版权)

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 1900-01-01 DOI: 10.1109/fccm51124.2021.00003

引用次数: 0

Welcome from the FCCM 2021 General Chair 欢迎2021年FCCM主席

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 1900-01-01 DOI: 10.1109/fccm51124.2021.00005

引用次数: 0