Microelectronic and MEMS Technologies最新文献_第10页

Control of organic contamination in CMOS manufacturing CMOS制造过程中有机污染的控制

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425279

J. Buegler, J. Frickinger, G. Zielonka, L. Pfitzner, H. Ryssel, M. Schottler

{"title":"Control of organic contamination in CMOS manufacturing","authors":"J. Buegler, J. Frickinger, G. Zielonka, L. Pfitzner, H. Ryssel, M. Schottler","doi":"10.1117/12.425279","DOIUrl":"https://doi.org/10.1117/12.425279","url":null,"abstract":"Yield control in manufacturing of microelectronic devices is closely related to defect control and contamination control. For a proper definition of process windows, e.g. maximum sit time or minimum quality of used process materials, the impact of different kinds of contamination on device performance has to be determined. This paper describes the outline of a strategy that was used for an estimation of the impact of organic airborne molecular contamination (AMC) on a realistic device process on the basis of selected experimental results: A manufacturing process was performed using intentionally contaminated substrates, monitoring measures were installed and baseline-levels were determined, time-dependent effects were detected, and process windows were defined on the basis of calculations. A gate-oxide integrity test was performed using intentionally contaminated silicon wafers. Contamination was performed via the gas phase using individual organic compounds. This test indicates that, besides the overall concentration of organic airborne molecular contamination, also the additional presence of small amounts of individual organic compounds has an effect on gate-oxide quality. The installation of measures for the monitoring of organic contamination using Gas-Chromatography/Mass-Spectrometry (GC/MS) or Time-of-Flight -- Secondary-Ion-Mass-Spectrometry (ToF-SIMS) lead to the observation that the deposition of organic contamination onto wafer surfaces can be a very fast process. Especially the preparation of blank samples is a procedure which is complicated by this effect. For an adequate definition of process windows it is necessary to estimate the time that remains until a freshly cleaned wafer is covered by a monolayer or organic contamination. This estimation was made on the basis of calculations using gas kinetic theory. Under standard cleanroom conditions the calculated time is in the range of minutes and is strongly depending on the adsorption probability of individual organic compounds and their individual concentrations.","PeriodicalId":429610,"journal":{"name":"Microelectronic and MEMS Technologies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134119741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Failure analysis of advanced packaging technologies using scanning acoustic microscopy 先进封装技术的扫描声学显微镜失效分析

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425281

J. Barton, A. Compagno, C. O'Mathúna

引用次数: 2

Mechanism and annihilation of shallow-trench-isolation-enhanced poly-mask-edge N+/P-well junction leakage 浅沟隔离增强多掩膜边缘N+/ p阱结漏的机理和湮灭

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425269

Kelvin Y. Doong, Sheng-che Lin, S. Hsieh, Binson Shen, Yu-Hao Yang, Peter Chen, C. Hsu

引用次数: 1

Observation of titanium-silicide via backside etching 硅化钛背面蚀刻的观察

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425264

E. Fleuren, Xiao-mei Zhang

{"title":"Observation of titanium-silicide via backside etching","authors":"E. Fleuren, Xiao-mei Zhang","doi":"10.1117/12.425264","DOIUrl":"https://doi.org/10.1117/12.425264","url":null,"abstract":"As IC device dimensions get smaller and smaller, not only do the formation and nature of silicide on the active silicon area become increasingly critical but so does the need for silicide inspection. The ability to inspect the silicide itself is especially important at electrical failure sites. In this paper we describe a straightforward sample preparation method which enables us, after removal of the substrate, to observe silicide from the back side using a scanning electron microscope (SEM). This method was used in combination with photo-emission microscopy (PEM) to localize the exact site of leaky junctions. With this method the silicide grains of different phases can easily be observed over large areas. It was found that in the leaking sites only the large grain C54 phase of TiSi2 was present and never the small grain C49 phase. In this paper we explain junction leakage in connection with phase transformation of titanium silicide, and show that the C54 phase which is normally desired for its low resistance may be problematic when the active Si areas are very small or when the titanium layer thickness is too thin. We also demonstrate that this method makes gate oxides, contact misalignment and other front-end issues readily observable.","PeriodicalId":429610,"journal":{"name":"Microelectronic and MEMS Technologies","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125482026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrated metrology: an enabler for advanced process control (APC) 集成计量:先进过程控制(APC)的推动者

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425280

C. Schneider, L. Pfitzner, H. Ryssel

引用次数: 9

Process-induced threshold voltage fluctuations on SOI fully depleted technology 过程诱导阈值电压波动的SOI完全耗尽技术

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425262

O. Potavin, A. Ahaitouf

{"title":"Process-induced threshold voltage fluctuations on SOI fully depleted technology","authors":"O. Potavin, A. Ahaitouf","doi":"10.1117/12.425262","DOIUrl":"https://doi.org/10.1117/12.425262","url":null,"abstract":"SOI devices have been shown to present better performances as compared to Bulk MOSFETs for low power-low voltage IC's. Thick film partially depleted SOI transistors have mainly been proposed up to now. However, for 0.1 and sub-0.1 micrometer devices or ultra low power devices, fully depleted thin and ultra-thin SOI MOSFETs with recess channel seem to be the best candidates. Indeed, those devices have been shown to present interesting properties in term of short channel effects, subthreshold swing and electron temperature. But one of the major bottleneck of SOI devices is the final film thickness control. According to the Lim and Fossum long channel model, the front interface threshold voltage is linearly dependent with the doping and the final silicon film thickness. Cumulative fluctuations of oxide growths and the non self alignment of the gate induce a strong threshold voltage variation on wafer and on a whole run. According to experimental results and 2D simulations the impact of the film thickness fluctuations and gate misalignment on the electrical performance will be presented. The maximum variations allowed to reach the design specifications will be extracted and finally a process windows will be defined.","PeriodicalId":429610,"journal":{"name":"Microelectronic and MEMS Technologies","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124830921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermoradiation modification of characteristics of silicon diffusion diodes 硅扩散二极管特性的热辐射改性

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425277

S. Makhkamov, Nigmatilla A. Tursunov, M. Ashurov, Z. M. Khakimov

引用次数: 0

Control and reduction of post-metal etch corrosion effects due to airborne molecular contamination 控制和减少空气中分子污染对金属蚀刻后腐蚀的影响

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425266

C. Morilla, P. Prieto, F. Barbado

{"title":"Control and reduction of post-metal etch corrosion effects due to airborne molecular contamination","authors":"C. Morilla, P. Prieto, F. Barbado","doi":"10.1117/12.425266","DOIUrl":"https://doi.org/10.1117/12.425266","url":null,"abstract":"Ionic contamination in microelectronic circuitry can have a detrimental effect on device reliability and yield. Post- aluminum etch corrosion has been considered a critical issue in dry plasma etching of aluminum. In this work, we review the actions taken to reduce the amount of defects due to Cl- induced corrosion in the metal lines at our manufacturing line in Lucent Technologies Madrid. Two approaches were followed in a parallel way: on one side manufacturing procedures were modified to reduce at the minimum the exposure of the unprotected metal lines to the clean room environment thus it is avoided any metal corrosion caused by a possible environmental contamination. The second working line was to improve the resistance to corrosion of the post-etched metal. With this aim, our efforts were focused on the passivation step just after the metal etch and prior the photoresist strip. The influence of several parameter settings of the passivation plasma on the resistance of the etched metal to corrosion has been studied. Accelerated corrosion tests were used to monitor the intrinsic metallization susceptibility of corrosion and chlorine and fluorine residuals content in the wafer were measured using ion-chromatography. It was found that a modification in the pressure, plasma power or duration of the passivation step could have a beneficial impact on the amount of chlorine residues left on the metal lines after etch and consequently an enhancement of their resistance to corrosion.","PeriodicalId":429610,"journal":{"name":"Microelectronic and MEMS Technologies","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124545926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Novel technique for reliability testing of silicon integrated circuits 硅集成电路可靠性测试新技术

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425265

P. LeMinh, H. Wallinga, P. Woerlee, A. van den Berg, J. Holleman

{"title":"Novel technique for reliability testing of silicon integrated circuits","authors":"P. LeMinh, H. Wallinga, P. Woerlee, A. van den Berg, J. Holleman","doi":"10.1117/12.425265","DOIUrl":"https://doi.org/10.1117/12.425265","url":null,"abstract":"We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer2 in sizes. Both positive and quasi-negative photoresists were employed. The resultant products are holes in the developed positive photoresist layer and mushroom- shaped spots in the quasi-negative one. Based on the photoresist decomposition energy dose, we could approximately calculate the light emitting power in the near UV range. Due to the proximity between the layer and the light source, the power is interpreted on a more accurate basis, which was a difficult task in previous research. The product sizes, dependent on the light emitting currents and exposure time, establish the core for a rough model that can be used for further application of this technique as a reliability analysis tool. One potential application is to detect and characterize regions of hot carriers on a VLSI circuit under operation for design improvement purpose.","PeriodicalId":429610,"journal":{"name":"Microelectronic and MEMS Technologies","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126940030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Increasing etch uniformity using in-line endpoint systems on complex spacer technology 在复杂的间隔器技术上使用在线端点系统提高蚀刻均匀性

Microelectronic and MEMS Technologies Pub Date : 2001-04-23 DOI: 10.1117/12.425267

D. K. Kempa, S. Hyland

引用次数: 0