2020 57th ACM/IEEE Design Automation Conference (DAC)最新文献_第3页

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model 基于概率资源模型的详细可达性驱动的三维全局路由

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218646

Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young

{"title":"CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model","authors":"Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young","doi":"10.1109/DAC18072.2020.9218646","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218646","url":null,"abstract":"Many competitive global routers adopt the technique of compressing the 3D routing space into 2D in order to handle today’s massive circuit scales. It has been shown as an effective way to shorten the routing time, however, quality will inevitably be sacrificed to different extents. In this paper, we propose two routing techniques that directly operate on the 3D routing space and can maximally utilize the 3D structure of a grid graph. The first technique is called 3D pattern routing, by which we combine pattern routing and layer assignment, and we are able to produce optimal solutions with respect to the patterns under consideration in terms of a cost function in wire length and routability. The second technique is called multi-level 3D maze routing. Two levels of maze routing with different cost functions and objectives are designed to maximize the routability and to search for the minimum cost path efficiently. Besides, we also designed a cost function that is sensitive to resources changes and a post-processing technique called patching that gives the detailed router more flexibility in escaping congested regions. Finally, the experimental results show that our global router outperforms all the contestants in the ICCAD’19 global routing contest.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"s3-44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130189378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Convergence-Aware Neural Network Training 收敛感知神经网络训练

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218518

Hyungjun Oh, Yongseung Yu, G. Ryu, Gunjoo Ahn, Yuri Jeong, Yongjun Park, Jiwon Seo

引用次数: 2

Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead 最小外围电路开销的内存神经网络计算算法/硬件协同设计

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218657

Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim

引用次数: 8

An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells * 非整数多高度单元格全局布局的高效EPIST算法*

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218504

Jianli Chen, Zhipeng Huang, Ye Huang, Wen-xing Zhu, Jun Yu, Yao-Wen Chang

{"title":"An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *","authors":"Jianli Chen, Zhipeng Huang, Ye Huang, Wen-xing Zhu, Jun Yu, Yao-Wen Chang","doi":"10.1109/DAC18072.2020.9218504","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218504","url":null,"abstract":"With the increasing design requirements of modern circuits, a standard-cell library often contains cells of different row heights to address various trade-offs among performance, power, and area. However, maintaining all standard cells with integer multiples of a single-row height could cause some area overheads and increase power consumption. In this paper, we present an analytical placer to directly consider a circuit design with non-integer multiple-height standard cells and additional layout constraints. The region of different cell heights is adaptively generated by the global placement result. In particular, an exact penalty iterative shrinkage and thresholding (EPIST) algorithm is employed to efficiently optimize the global placement problem. The convergence of the algorithm is proved, and the acceleration strategy is proposed to improve the performance of our algorithm. Compared with the state-of-the-art works, experimental results based on the 2017 CAD Contest at ICCAD benchmarks show that our algorithm achieves the best wirelength and area for every benchmark. In particular, our proposed EPIST algorithm provides a new direction for effectively solving large-scale nonlinear optimization problems with non-smooth terms, which are often seen in real-world applications.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132779115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Learning to Quantize Deep Neural Networks: A Competitive-Collaborative Approach 学习量化深度神经网络:一种竞争-协作的方法

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218576

Md Fahim Faysal Khan, Mohammad Mahdi Kamani, M. Mahdavi, V. Narayanan

引用次数: 11

Eliminating Redundant Computation in Noisy Quantum Computing Simulation 噪声量子计算模拟中冗余计算的消除

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218666

Gushu Li, Yufei Ding, Yuan Xie

{"title":"Eliminating Redundant Computation in Noisy Quantum Computing Simulation","authors":"Gushu Li, Yufei Ding, Yuan Xie","doi":"10.1109/DAC18072.2020.9218666","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218666","url":null,"abstract":"Noisy Quantum Computing (QC) simulation on a classical machine is very time consuming since it requires Monte Carlo simulation with a large number of error-injection trials to model the effect of random noises. Orthogonal to existing QC simulation optimizations, we aim to accelerate the simulation by eliminating the redundant computation among those Monte Carlo simulation trials. We observe that the intermediate states of many trials can often be the same. Once these states are computed in one trial, they can be temporarily stored and reused in other trials. However, storing such states will consume significant memory space. To leverage the shared intermediate states without introducing too much storage overhead, we propose to statically generate and analyze the Monte Carlo simulation simulation trials before the actual simulation. Those trials are reordered to maximize the overlapped computation between two consecutive trials. The states that cannot be reused in follow-up simulation are dropped, so that we only need to store a few states. Experiment results show that the proposed optimization scheme can save on average 80% computation with only a small number of state vectors stored. In addition, the proposed simulation scheme demonstrates great scalability as more computation can be saved with more simulation trials or on future QC devices with reduced error rates.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130979422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Don’t-Care-Based Node Minimization for Threshold Logic Networks 阈值逻辑网络中基于不关心的节点最小化

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218506

Yung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng

{"title":"Don’t-Care-Based Node Minimization for Threshold Logic Networks","authors":"Yung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng","doi":"10.1109/DAC18072.2020.9218506","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218506","url":null,"abstract":"Threshold logic re-attracts researchers’ attention recently due to the advancement of hardware realization techniques and its applications to deep learning. In the past decade, several design automation techniques for threshold logic have been proposed, such as logic synthesis and logic optimization. Although they are effective, threshold logic network (TLN) optimization based on don’t cares has not been well studied. In this paper, we propose a don’t-care-based node minimization scheme for TLNs. We first present a sufficient condition for don’t cares to exist and a logic-implication-based method to identify the don’t cares of a threshold logic gate (TLG). Then, we transform the problem of TLG minimization with don’t cares to an integer linear programming problem, and present a method to compute the necessary constraints for the ILP formulation. We apply the proposed optimization scheme to two set of TLNs generated by the state-of-the-art synthesis technique. The experimental results show that, for the two sets, it achieves an average of 11% and 19% of area reduction in terms of the sum of the weights and threshold values without overhead on the TLG count and logic depth. Additionally, it completes the optimization of most TLNs within one minute.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132449905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Improving the Concurrency Performance of Persistent Memory Transactions on Multicores 提高多核持久内存事务的并发性能

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218554

Qing Wang, Youyou Lu, Zhongjie Wu, Fan Yang, J. Shu

引用次数: 1

Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle Applications 新兴互联和自动驾驶汽车应用的车辆和边缘计算

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218618

S. Baidya, Yu-Jen Ku, Hengyu Zhao, Jishen Zhao, S. Dey

引用次数: 23

A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures 基于芯片的异构多核系统设计

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218654

Hao Zheng, Ke Wang, A. Louri

{"title":"A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures","authors":"Hao Zheng, Ke Wang, A. Louri","doi":"10.1109/DAC18072.2020.9218654","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218654","url":null,"abstract":"Heterogeneous manycore architectures are deployed to simultaneously run multiple and diverse applications. This requires various computing capabilities (CPUs, GPUs, and accelerators), and an efficient network-on-chip (NoC) architecture to concurrently handle diverse application communication behavior. However, supporting the concurrent communication requirements of diverse applications is challenging due to the dynamic application mapping, the complexity of handling distinct communication patterns and limited on-chip resources. In this paper, we propose Adapt-NoC, a versatile and flexible NoC architecture for chiplet-based manycore architectures, consisting of adaptable routers and links. Adapt-NoC can dynamically allocate disjoint regions of the NoC, called subNoCs, for concurrently-running applications, each of which can be optimized for different communication behavior. The adaptable routers and links are capable of providing various subNoC topologies, satisfying different latency and bandwidth requirements of various traffic patterns (e.g. all-to-all, one-to-many). Full system simulation shows that AdaptNoC can achieve 31% latency reduction, 24% energy saving and 10% execution time reduction on average, when compared to prior designs.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115020590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16