2020 57th ACM/IEEE Design Automation Conference (DAC)最新文献_第10页

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM 工艺:自旋电子计算RAM中的高分辨率FFT加速器

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218673

Hüsrev Cılasun, Salonik Resch, Z. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas J. Peterson, Jianping Wang, S. Sapatnekar, Ulya R. Karpuzcu

引用次数: 11

Impeccable Circuits II 完美电路II

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218615

Aein Rezaei Shahmirzadi, Shahram Rasoolzadeh, A. Moradi

引用次数: 28

TrojDRL: Evaluation of Backdoor Attacks on Deep Reinforcement Learning TrojDRL:评估对深度强化学习的后门攻击

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218663

Panagiota Kiourti, Kacper Wardega, Susmit Jha, Wenchao Li

引用次数: 50

SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures 用于容错深度神经网络架构的在线加速框架

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218697

N. Khoshavi, A. Roohi, Connor Broyles, S. Sargolzaei, Yu Bi, D. Pan

引用次数: 16

DPCP-p: A Distributed Locking Protocol for Parallel Real-Time Tasks 并行实时任务的分布式锁定协议

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218584

Maolin Yang, Zewei Chen, Xu Jiang, Nan Guan, Hang Lei

引用次数: 9

SAT-Sweeping Enhanced for Logic Synthesis sat扫描增强逻辑合成

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218691

L. Amarù, F. Marranghello, Eleonora Testa, Christopher Casares, V. Possani, Jiong Luo, P. Vuillod, A. Mishchenko, G. Micheli

{"title":"SAT-Sweeping Enhanced for Logic Synthesis","authors":"L. Amarù, F. Marranghello, Eleonora Testa, Christopher Casares, V. Possani, Jiong Luo, P. Vuillod, A. Mishchenko, G. Micheli","doi":"10.1109/DAC18072.2020.9218691","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218691","url":null,"abstract":"SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification and synthesis applications within EDA. In this paper, we focus on the development of a highly efficient, synthesis-oriented, SAT-sweeping engine. We introduce a new algorithm to guide initial simulation, which strongly reduces the number of false candidates for merge, thus increasing the computational efficiency of the sweeper. We revisit the SAT-sweeping flow in light of practical considerations for synthesis, with the aim of proving all valid merges and ensuring fast execution. Experimental results confirm remarkable speedup deriving from our methodology, up to 10× for large combinational networks, and better QoR as compared to previous SAT-sweeping implementation. Embedded in a commercial synthesis flow, our proposes SAT-sweeper enables area and power savings of 1.98% and 1.81%, respectively, with neutral timing at negligible runtime overhead, over 36 testcases.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A-QED Verification of Hardware Accelerators 硬件加速器的A-QED验证

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218715

Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, J. Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, S. Mitra

引用次数: 10

Tier-Scrubbing: An Adaptive and Tiered Disk Scrubbing Scheme with Improved MTTD and Reduced Cost 层刷洗:一种改进MTTD和降低成本的自适应分层磁盘刷洗方案

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218551

Ji Zhang, Yuanzhang Wang, Yangtao Wang, Ke Zhou, Sebastian Schelter, Ping Huang, Bin Cheng, Yongguang Ji

{"title":"Tier-Scrubbing: An Adaptive and Tiered Disk Scrubbing Scheme with Improved MTTD and Reduced Cost","authors":"Ji Zhang, Yuanzhang Wang, Yangtao Wang, Ke Zhou, Sebastian Schelter, Ping Huang, Bin Cheng, Yongguang Ji","doi":"10.1109/DAC18072.2020.9218551","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218551","url":null,"abstract":"Sector errors are a common type of error in modern disks. A sector error that occurs during I/O operations might cause inaccessibility of an application. Even worse, it could result in permanent data loss if the data is being reconstructed, and thereby severely affects the reliability of a storage system. Many disk scrubbing schemes have been proposed to solve this problem. However, existing approaches have several limitations. First, schemes use machine learning (ML) to predict latent sector errors (LSEs), but only leverage a single snapshot of training data to make a prediction, and thereby ignore sequential dependencies between different statuses of a hard disk over time. Second, they accelerate the scrubbing at a fixed rate based on the results of a binary classification model, which may result in unnecessary increases in scrubbing cost. Third, they naively accelerate the scrubbing of the full disk which has LSEs based on the predictive results, but neglect partial high-risk areas (the areas that have a higher probability of encountering LSEs). Lastly, they do not employ strategies to scrub these high-risk areas in advance based on I/O accesses patterns, in order to further increase the efficiency of scrubbing.We address these challenges by designing a Tier-Scrubbing (TS) scheme that combines a Long Short-Term Memory (LSTM) based Adaptive Scrubbing Rate Controller (ASRC), a module focusing on sector error locality to locate high-risk areas in a disk, and a piggyback scrubbing strategy to improve the reliability of a storage system. Our evaluation results on realistic datasets and workloads from two real world data centers demonstrate that TS can simultaneously decrease the Mean-Time-To-Detection (MTTD) by about 80% and the scrubbing cost by 20%, compared to a state-of-the-art scrubbing scheme.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131911869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning Acceleration

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218508

Huili Chen, Rosario Cammarota, Felipe Valencia, F. Regazzoni, F. Koushanfar

{"title":"AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning Acceleration","authors":"Huili Chen, Rosario Cammarota, Felipe Valencia, F. Regazzoni, F. Koushanfar","doi":"10.1109/DAC18072.2020.9218508","DOIUrl":"https://doi.org/10.1109/DAC18072.2020.9218508","url":null,"abstract":"Privacy-preserving machine learning (PPML) is driven by the emerging adoption of Machine Learning as a Service (MLaaS). In a typical MLaaS system, the end-user sends his personal data to the service provider and receives the corresponding prediction output. However, such interaction raises severe privacy concerns about both the user’s proprietary data and the server’s ML model. PPML integrates cryptographic primitives such as Multi-Party Computation (MPC) and/or Homomorphic Encryption (HE) into ML services to resolve the privacy issue. However, existing PPML solutions have not been widely deployed in practice since: (i) Privacy protection comes at the cost of additional computation and/or communication overhead; (ii) Adapting PPML to different front-end frameworks and back-end hardware incurs prohibitive engineering cost.We propose AHEC, the first automated, end-to-end HE compiler for efficient PPML inference. Leveraging the capability of Domain Specific Languages (DSLs), AHEC enables automated generation and optimization of HE kernels across diverse types of hardware platforms and ML frameworks. We perform extensive experiments to investigate the performance of AHEC from different abstraction levels: HE operations, HE-based ML kernels, and neural network layers. Empirical results corroborate that AHEC achieves superior runtime reduction compared to the state-of-the-art solutions built from static HE libraries.","PeriodicalId":428807,"journal":{"name":"2020 57th ACM/IEEE Design Automation Conference (DAC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133487350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies 新兴技术扇出边界逻辑综合的可扩展方法

2020 57th ACM/IEEE Design Automation Conference (DAC) Pub Date : 2020-07-01 DOI: 10.1109/DAC18072.2020.9218500

He-Teng Zhang, J. H. Jiang

引用次数: 1