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International Workshop on Power and Timing Modeling, Optimization and Simulation最新文献

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Timing Modeling of Flipflops Considering Aging Effects 考虑老化效应的人字拖时序建模
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_7
Ning Chen, Bing Li, Ulf Schlichtmann
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引用次数: 1
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode 通过在待机模式下给出随机扫描矢量来缓解NBTI
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_16
Toshihiro Kameda, Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
{"title":"NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode","authors":"Toshihiro Kameda, Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye","doi":"10.1007/978-3-642-24154-3_16","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_16","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating 并行时钟门控和功率门控的子行睡眠晶体管插入
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_22
K. Lingasubramanian, A. Calimera, A. Macii, E. Macii, M. Poncino
{"title":"Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating","authors":"K. Lingasubramanian, A. Calimera, A. Macii, E. Macii, M. Poncino","doi":"10.1007/978-3-642-24154-3_22","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_22","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134580733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits 降低寄存器电路时钟功率的统一门控触发器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_24
Takumi Okuhira, T. Ishihara
{"title":"Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits","authors":"Takumi Okuhira, T. Ishihara","doi":"10.1007/978-3-642-24154-3_24","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_24","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134281469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique 基于MTCMOS技术设计SOC应用的CBLPRP优化方法
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_15
Henry X. F. Huang, Steven Shen, J. Kuo
{"title":"Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique","authors":"Henry X. F. Huang, Steven Shen, J. Kuo","doi":"10.1007/978-3-642-24154-3_15","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_15","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133037402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Pass Transistor Operation Modeling for Nanoscale Technologies 通过纳米技术晶体管操作建模
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_6
Panagiotis Chaourani, I. Pappas, S. Nikolaidis, A. Rjoub
{"title":"Pass Transistor Operation Modeling for Nanoscale Technologies","authors":"Panagiotis Chaourani, I. Pappas, S. Nikolaidis, A. Rjoub","doi":"10.1007/978-3-642-24154-3_6","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_6","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130279052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High Level Synthesis of Asynchronous Circuits from Data Flow Graphs 基于数据流图的异步电路高级综合
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_32
R. V. Leuken, T. V. Leeuwen, H.L. Arriens
{"title":"High Level Synthesis of Asynchronous Circuits from Data Flow Graphs","authors":"R. V. Leuken, T. V. Leeuwen, H.L. Arriens","doi":"10.1007/978-3-642-24154-3_32","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_32","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114667073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution 基于广义极值分布的芯片级统计泄漏功率估计
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_18
A. Khosropour, H. Aghababa, A. Afzali-Kusha, B. Forouzandeh
{"title":"Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution","authors":"A. Khosropour, H. Aghababa, A. Afzali-Kusha, B. Forouzandeh","doi":"10.1007/978-3-642-24154-3_18","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_18","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115508487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures 用于3D多处理器架构热优化的功耗分析引导地板规划器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_2
Ignacio Arnaldo, J. L. Risco-Martín, J. Ayala, J. Hidalgo
{"title":"Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures","authors":"Ignacio Arnaldo, J. L. Risco-Martín, J. Ayala, J. Hidalgo","doi":"10.1007/978-3-642-24154-3_2","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_2","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125208213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Secure D Flip-Flop against Side Channel Attacks 一种对抗侧信道攻击的安全D触发器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_33
Bruno Vaquie, S. Tiran, P. Maurine
{"title":"A Secure D Flip-Flop against Side Channel Attacks","authors":"Bruno Vaquie, S. Tiran, P. Maurine","doi":"10.1007/978-3-642-24154-3_33","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_33","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122201503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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