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International Workshop on Power and Timing Modeling, Optimization and Simulation最新文献

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Architecture Extensions for Efficient Management of Scratch-Pad Memory 高效管理刮刮板内存的架构扩展
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_5
J. Busquets-Mataix, Carlos Catalá, A. M. Campoy
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引用次数: 1
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits 三维集成电路谐振时钟配电网的设计
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_27
S. R. Omam, V. Pavlidis, G. Micheli
{"title":"Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits","authors":"S. R. Omam, V. Pavlidis, G. Micheli","doi":"10.1007/978-3-642-24154-3_27","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_27","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging 包括参数变化和晶体管老化的波形精确定时模拟器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_20
Christoph Knoth, C. Uphoff, S. Kiesel, Ulf Schlichtmann
{"title":"SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging","authors":"Christoph Knoth, C. Uphoff, S. Kiesel, Ulf Schlichtmann","doi":"10.1007/978-3-642-24154-3_20","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_20","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132079988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study 不同资源可用性的最坏情况温度分析:案例研究
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_29
Lars Schor, Hoeseok Yang, Iuliana Bacivarov, L. Thiele
{"title":"Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study","authors":"Lars Schor, Hoeseok Yang, Iuliana Bacivarov, L. Thiele","doi":"10.1007/978-3-642-24154-3_29","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_29","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115392613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts 基于UPF标准概念的片上系统功耗感知事务级模型方法
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_23
Ons Mbarek, A. Pegatoquet, M. Auguin
{"title":"A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts","authors":"Ons Mbarek, A. Pegatoquet, M. Auguin","doi":"10.1007/978-3-642-24154-3_23","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_23","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"35 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116598806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores 基于代理的三维多核实时I/O通信重定位热管理
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_12
T. Ebi, Holm Rauchfuss, A. Herkersdorf, J. Henkel
{"title":"Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores","authors":"T. Ebi, Holm Rauchfuss, A. Herkersdorf, J. Henkel","doi":"10.1007/978-3-642-24154-3_12","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_12","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116735354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Variability-Speed-Consumption Trade-off in Near Threshold Operation 近阈值操作中的可变性-速度-消耗权衡
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_31
M. Slimani, F. Silveira, Philippe Matherat
{"title":"Variability-Speed-Consumption Trade-off in Near Threshold Operation","authors":"M. Slimani, F. Silveira, Philippe Matherat","doi":"10.1007/978-3-642-24154-3_31","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_31","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130438386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits 数字电路能量优化栅极尺寸的一种快速方法
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_1
M. Aktan, D. Baran, V. Oklobdzija
{"title":"A Quick Method for Energy Optimized Gate Sizing of Digital Circuits","authors":"M. Aktan, D. Baran, V. Oklobdzija","doi":"10.1007/978-3-642-24154-3_1","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_1","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115230287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer 控制精度的纯数字方波频率合成器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2010-09-07 DOI: 10.1007/978-3-642-17752-1_21
A. K. Oudjida, A. Liacha, M. L. Berrandjia, R. Tiar
{"title":"Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer","authors":"A. K. Oudjida, A. Liacha, M. L. Berrandjia, R. Tiar","doi":"10.1007/978-3-642-17752-1_21","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_21","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115587196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk 考虑过渡活动和串扰的片上系统互连的系统级功率估计
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2010-09-07 DOI: 10.1007/978-3-642-17752-1_3
Martin Gag, Tim Wegner, D. Timmermann
{"title":"System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk","authors":"Martin Gag, Tim Wegner, D. Timmermann","doi":"10.1007/978-3-642-17752-1_3","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_3","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124828275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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