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International Workshop on Power and Timing Modeling, Optimization and Simulation最新文献

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Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling 基于DVFS和变流量液冷的3D mpsoc凸型热管理
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_34
Francesco Zanini, David Atienza Alonso, G. Micheli
{"title":"Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling","authors":"Francesco Zanini, David Atienza Alonso, G. Micheli","doi":"10.1007/978-3-642-24154-3_34","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_34","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134324130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improving the Robustness of Self-timed SRAM to Variable Vdds 提高自定时SRAM对可变vdd的鲁棒性
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_4
A. Baz, D. Shang, Fei Xia, A. Yakovlev, A. Bystrov
{"title":"Improving the Robustness of Self-timed SRAM to Variable Vdds","authors":"A. Baz, D. Shang, Fei Xia, A. Yakovlev, A. Bystrov","doi":"10.1007/978-3-642-24154-3_4","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_4","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133536118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels 使用智能高效垂直通道的3D片上网络的功耗和面积优化
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_28
A. Rahmani, Kameswar Rao Vaddina, P. Liljeberg, J. Plosila, H. Tenhunen
{"title":"Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels","authors":"A. Rahmani, Kameswar Rao Vaddina, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1007/978-3-642-24154-3_28","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_28","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115023703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs 用于数字ip的片上全数字pv监控体系结构
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_17
H. K. Alidash, A. Calimera, A. Macii, E. Macii, M. Poncino
{"title":"An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs","authors":"H. K. Alidash, A. Calimera, A. Macii, E. Macii, M. Poncino","doi":"10.1007/978-3-642-24154-3_17","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_17","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122133708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization 基于概率逻辑最小化的容错简化电路
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_21
L. Avinash, C. Enz, K. Palem, C. Piguet
{"title":"Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization","authors":"L. Avinash, C. Enz, K. Palem, C. Piguet","doi":"10.1007/978-3-642-24154-3_21","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_21","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129552135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs 基于Xilinx Virtex fpga的TMR系统自参考洗涤器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_14
I. Herrera-Alzu, M. López-Vallejo
{"title":"Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs","authors":"I. Herrera-Alzu, M. López-Vallejo","doi":"10.1007/978-3-642-24154-3_14","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_14","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing 生物医学信号处理中单核和多核处理器方法的功耗/性能探索
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_11
A. Dogan, David Atienza Alonso, A. Burg, Igor Loi, L. Benini
{"title":"Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing","authors":"A. Dogan, David Atienza Alonso, A. Burg, Igor Loi, L. Benini","doi":"10.1007/978-3-642-24154-3_11","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_11","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129014282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A System Level Approach to Multi-core Thermal Sensors Calibration 多核热传感器标定的系统级方法
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_3
Andrea Bartolini, MohammadSadegh Sadri, Francesco Beneventi, M. Cacciari, A. Tilli, L. Benini
{"title":"A System Level Approach to Multi-core Thermal Sensors Calibration","authors":"Andrea Bartolini, MohammadSadegh Sadri, Francesco Beneventi, M. Cacciari, A. Tilli, L. Benini","doi":"10.1007/978-3-642-24154-3_3","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_3","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122489222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology 基于CMOS/磁混合技术的低功耗数字电路超紧凑非易失性触发器
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_9
G. D. Pendina, K. Torki, G. Prenat, Yoann Guillemenet, L. Torres
{"title":"Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology","authors":"G. D. Pendina, K. Torki, G. Prenat, Yoann Guillemenet, L. Torres","doi":"10.1007/978-3-642-24154-3_9","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_9","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115994825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Framework for Architecture-Level Exploration of 3-D FPGA Platforms 三维FPGA平台的架构级探索框架
International Workshop on Power and Timing Modeling, Optimization and Simulation Pub Date : 2011-09-26 DOI: 10.1007/978-3-642-24154-3_30
H. Sidiropoulos, K. Siozios, D. Soudris
{"title":"A Framework for Architecture-Level Exploration of 3-D FPGA Platforms","authors":"H. Sidiropoulos, K. Siozios, D. Soudris","doi":"10.1007/978-3-642-24154-3_30","DOIUrl":"https://doi.org/10.1007/978-3-642-24154-3_30","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114854724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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