2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)最新文献_第2页

Run-time power and performance scaling with CPU-FPGA hybrids CPU-FPGA混合的运行时功耗和性能扩展

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880158

J. Núñez-Yáñez, A. Beldachi

引用次数: 11

Automated thresholding for low-complexity corner detection 自动阈值低复杂度角检测

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880164

N. Ramakrishnan, Meiqing Wu, S. Lam, T. Srikanthan

{"title":"Automated thresholding for low-complexity corner detection","authors":"N. Ramakrishnan, Meiqing Wu, S. Lam, T. Srikanthan","doi":"10.1109/AHS.2014.6880164","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880164","url":null,"abstract":"Widely-used corner detectors such as Shi-Tomasi and Harris necessitate the selection of a threshold parameter manually in order to identify good quality corners. The recent attempts based on trial-and-error methods for threshold setting are time-consuming, making them unsuitable for low-cost and embedded video processing applications. In this paper we propose a novel automated thresholding technique for Shi-Tomasi and Harris corner detectors based on an iterative pruning strategy. The proposed pruning strategy involves the rapid extraction of potential corner regions and their evaluation for detecting corners. This pruning strategy is applied iteratively until the required number of corners is identified without necessitating the selection of the threshold parameter. As the complex corner measure computations of the Shi-Tomasi and Harris detectors are only applied to very small regions selected by the proposed pruning method, significant savings in computation is also achieved. In addition, the pruning strategy is computationally simpler, making it suitable for deployment in low cost and embedded applications. Our evaluations on the NiOS-II embedded platform show that the proposed automated thresholding technique is able to achieve an average speedup of 67% in Shi-Tomasi and 51% in Harris, with almost no loss in accuracy. The proposed method to identify corners without the manual selection of a threshold parameter makes it ideal for corner detection on a wide range of imagery where the quantity and quality of corners is not known a priori such as in video processing applications.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134085408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A compact realization of an n-bit quantum carry skip adder circuit with optimal delay 具有最佳延迟的n位量子进位跳加器电路的紧凑实现

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880187

N. J. Lisa, H. Babu

{"title":"A compact realization of an n-bit quantum carry skip adder circuit with optimal delay","authors":"N. J. Lisa, H. Babu","doi":"10.1109/AHS.2014.6880187","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880187","url":null,"abstract":"This paper presents the design of a novel n-bit carry skip adder by its core components using quantum logic. The novelty of the proposed adder is that it considers a new design with optimal delay. Moreover, it is the first time in quantum circuit synthesis that the quantum realization of a carry skip adder is shown in terms of quantum gates, power and area, etc. Our proposed quantum multiplexer gate (QMG) and quantum comparison gate (QCG) perfectly operates as a 2-to-1 MUX and a comparison circuit, respectively. Using QMG and QCG as a unit element of construction, we optimize the design of Carry Skip Adder. A generalized architecture of the proposed n-bit adder has also been presented. The comparative study shows that the proposed quantum carry skip adder performs better than the existing carry skip adders with the increasing number of bits; e.g., the proposed 128-bit carry skip adder improves 40.96% on number of quantum gates, 48.19% on delay, 22.22% on garbage outputs and 40.96% on area and power over the existing best one. In addition, we also simulate the proposed adder using Microwind DSCH 3.5 and QuIDDPro software to show the correctness of the circuit.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127779967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Soft error mitigation through selection of noninvert implication paths 通过选择非反转隐含路径来减少软误差

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880161

Bin Zhou, T. Srikanthan, Wei Zhang

引用次数: 5

Efficient reconfiguration of processing modules on FPGAs for space instruments 空间仪器fpga处理模块的高效重构

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880153

S. Fekete, B. Fiethe, Stephan Friedrichs, H. Michalik, Christos Orlis

{"title":"Efficient reconfiguration of processing modules on FPGAs for space instruments","authors":"S. Fekete, B. Fiethe, Stephan Friedrichs, H. Michalik, Christos Orlis","doi":"10.1109/AHS.2014.6880153","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880153","url":null,"abstract":"We consider optimization techniques for a problem that requires a valid scheduling and allocation of tasks on Field Programmable Gate Arrays (FPGAs). A concrete application on a scientific space instrument arises in the context of ESA's Solar Orbiter mission; making use of dynamic reconfiguration allows a good and flexible use of resources, but the resulting packing and scheduling problems in the presence of inhomogeneous allocation resources are quite challenging. In our scenario, modules are described by three parameters: their resource demands for different types of resources, their priority, and their clock frequency. These are to be allocated on an FPGA that provides a number of different resources that are available at specific locations. We first present an Integer Program that partitions the tasks in such a way that all constraints can be met and the reconfiguration overhead is minimized, and then give methods for allocating the processing modules of the partitioned tasks on the FPGA. We evaluate our methods on a real application of the Solar Orbiter PHI instrument. The results obtained indicate computational efficiency and a remarkable solution quality.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130513334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Region adaptive digital image watermarking system using DWT-SVD algorithm 区域自适应数字图像水印系统采用DWT-SVD算法

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880177

Chunlin Song, P. Xiao, S. Sudirman, M. Merabti

引用次数: 9

Detection of Silent Data Corruption in fault-tolerant distributed systems on board spacecraft 航天器上容错分布式系统中静默数据损坏的检测

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880178

Muhammad Fayyaz, T. Vladimirova

引用次数: 3

Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA 考虑2D可重构FPGA相关任务调度中的重构开销

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880151

Quang-Hai Khuat, D. Chillet, M. Hübner

{"title":"Considering reconfiguration overhead in scheduling of dependent tasks on 2D reconfigurable FPGA","authors":"Quang-Hai Khuat, D. Chillet, M. Hübner","doi":"10.1109/AHS.2014.6880151","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880151","url":null,"abstract":"Configuration prefetching is known as an effective technique for hiding the reconfiguration delay of hardware accelerators in Partial Region FPGA. In prefetching, a hardware task can be loaded as soon as possible even if it cannot execute immediately after its reconfiguration due to the involvement of dependencies with other tasks. But due to the access in advance, the configuration delay is hidden. This method can be compared with a software prefetching in the processor domain. However, in the context of reconfigurable architecture, the difficulties come from the dependencies of prefetching with task scheduling and placement aspect. In this paper, we introduce an run-time spatio-temporal scheduling heuristic for dependent tasks executed on 2D heterogeneous FPGA. The objective is to reduce the reconfiguration delay of tasks, thus minimize the total execution time of an application. To achieve it, our proposed heuristic tries to prefetch tasks as early as possible while considering two factors: the priority of new tasks to be loaded and the placement decision to avoid conflicts among tasks. The experiments show that our heuristic reduces significantly the overall execution time by 22% compared to a non-prefetching method and approximately 5% compared to other prefetching methods.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129986149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Towards an adaptive network centric distributed time- and space partitioned platform architecture 以网络为中心的自适应分布式时空分区平台体系结构

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880172

C. Fidi, H. Herpel

引用次数: 0

Software defined radios for small satellites 用于小型卫星的软件无线电

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880174

Mamatha R. Maheshwarappa, C. Bridges

{"title":"Software defined radios for small satellites","authors":"Mamatha R. Maheshwarappa, C. Bridges","doi":"10.1109/AHS.2014.6880174","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880174","url":null,"abstract":"Clusters, constellations, formations, or `swarms' of small satellites are fast becoming a way to perform scientific and technological missions more affordably. As objectives of these missions become more ambitious, there are still problems in increasing the number of communication windows, supporting multiple signals, and increasing data rates over reliable intersatellite and ground links to Earth. Also, there is a shortage of available frequencies in the 2 m and 70 cm bands due to rapid increase in the number of CubeSats orbiting the Earth - leading to further regulatory issues. Existing communication systems and radio signal processing Intellectual Property (IP) cores cannot fully address these challenges. One of the possible strategies to solve these issues is by equipping satellites with a Software Defined Radio (SDR). SDR is a key area to realise various software implementations which enable an adaptive and reconfigurable communication system without changing any hardware device or feature. This paper proposes a new SDR architecture which utilises a combination of Field Programmable Gate Array (FPGA) and field programmable Radio Frequency (RF) transceiver to solve back-end and front- end challenges and thereby enabling reception of multiple signals or satellites using single user equipment.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125075686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46