Run-time power and performance scaling with CPU-FPGA hybrids

Abstract

This paper investigates how a wide dynamic range of performance and power levels can be obtained in commercially available state-of-the-art hybrid FPGAs that include ARM embedded processors and independent power domains. Adaptive voltage and frequency scaling obtained with embedded in-situ detectors in a closed loop configuration is employed to scale performance and power in the FPGA fabric under processor control. The initial results are based on a high-performance motion estimation processor mapped to the FPGA fabric and show that it is possible to obtain energy savings higher than 60% or alternatively double performance at nominal energy. The available voltage and frequency margins in the device create a large number of performance and energy states with scaling possible at run-time with low overheads.