2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)最新文献

Space Wireless Sensor Networks for planetary exploration: Node and network architectures 用于行星探测的空间无线传感器网络:节点和网络架构

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880175

Pedro Rodrigues, André Oliveira, G. Oddi, F. Liberati, Francisco Alvarez, R. Cabás, T. Vladimirova, X. Zhai, Hongyuan Jing, M. Crosnier

引用次数: 12

The upset-fault-observer: A concept for self-healing adaptive fault tolerance 故障-故障-观察者:一种自愈自适应容错的概念

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880163

Byron Navas, Johnny Öberg, I. Sander

{"title":"The upset-fault-observer: A concept for self-healing adaptive fault tolerance","authors":"Byron Navas, Johnny Öberg, I. Sander","doi":"10.1109/AHS.2014.6880163","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880163","url":null,"abstract":"Advancing integration reaching atomic-scales makes components highly defective and unstable during lifetime. This demands paradigm shifts in electronic systems design. FPGAs are particularly sensitive to cosmic and other kinds of radiations that produce single-event-upsets (SEU) in configuration and internal memories. Typical fault-tolerance (FT) techniques combine triple-modular-redundancy (TMR) schemes with run-time-reconfiguration (RTR). However, even the most successful approaches disregard the low suitability of fine-grain redundancy in nano-scale design, poor scalability and programmability of application specific architectures, small performance-consumption ratio of board-level designs, or scarce optimization capability of rigid redundancy structures. In that context, we introduce an innovative solution that exploits the flexibility, reusability, and scalability of a modular RTR SoC approach and reuse existing RTR IP-cores in order to assemble different TMR schemes during run-time. Thus, the system can adaptively trigger the adequate self-healing strategy according to execution environment metrics and user-defined goals. Specifically the paper presents: (a) the upset-fault-observer (UFO), an innovative run-time self-test and recovery strategy that delivers FT on request over several function cores but saves the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles, (b) run-time reconfigurable TMR schemes and self-repair mechanisms, and (c) an adaptive software organization model to manage the proposed FT strategies.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125750424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A hierarchical fault tolerant system on the PAnDA device with low disruption 在PAnDA设备上建立一个低中断的分层容错系统

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880160

David M. R. Lawson, James Alfred Walker, M. Trefzer, S. Bale, A. Tyrrell

{"title":"A hierarchical fault tolerant system on the PAnDA device with low disruption","authors":"David M. R. Lawson, James Alfred Walker, M. Trefzer, S. Bale, A. Tyrrell","doi":"10.1109/AHS.2014.6880160","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880160","url":null,"abstract":"This paper presents the concept of hierarchical reconfiguration strategies that can be applied to a circuit on a reconfigurable architecture to change the implementation without changing the functionality, and their use to overcome faults in a source agnostic way. The Programmable Analogue and Digital Array (PAnDA) is a novel FPGA-like reconfigurable architecture, with configuration options below the digital layer. The PAnDA architecture includes symmetry and homogeneity at multiple levels of the configuration hierarchy. These properties could be exploited to take advantage of redundant resources in the event of a fault. To demonstrate this, faults are injected, repeatedly and at random, to a configured logic function until functionality breaks. Reconfiguration strategies are then applied at random in repeated steps to the faulty circuit until functionality is restored (or a set number of steps have been taken). An experiment is conducted to investigate whether controlling the probability of picking a particular strategy at each step can improve the average efficiency of fault recovery for a given function. It is found that the average number of steps required to fix a fault can be reduced while it is possible to increase the average number of circuits that can be fixed.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116002378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Learning engine for cognitive radio based on the immune principle 基于免疫原理的认知无线电学习引擎

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880179

Rui Yao, Kun He, Yanmei Sun, You-ren Wang

引用次数: 5

Airborne demonstration of FPGA implementation of Fast Lossless hyperspectral data compression system 快速无损高光谱数据压缩系统的FPGA机载演示

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880188

D. Keymeulen, N. Aranki, A. Bakhshi, H. Luong, C. Sarture, D. Dolman

{"title":"Airborne demonstration of FPGA implementation of Fast Lossless hyperspectral data compression system","authors":"D. Keymeulen, N. Aranki, A. Bakhshi, H. Luong, C. Sarture, D. Dolman","doi":"10.1109/AHS.2014.6880188","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880188","url":null,"abstract":"Efficient on-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed `Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A prototype of the compressor (and decompressor) of the algorithm is available in software, but this implementation may not meet speed and real-time requirements of some space applications. This paper describes a hardware implementation of the `Modified Fast Lossless' compression algorithm for push broom instruments on a Field Programmable Gate Array (FPGA). The FPGA implementation has been integrated into the Next Generation Data Capture System (NGDCS) avionics system for the Airborne Visible/ Infrared Imaging Spectrometer Next Generation (AVIRISng). The NGDCS includes two airborne hardware platforms which were flown on a Twin Otter aircraft: a National Instrument PXI and the Alpha Data Systems. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex V and VI families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for Space applications.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128180723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Novel PCA based pixel-level multi-focus image fusion algorithm 一种基于PCA的像素级多焦点图像融合算法

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880169

Hongyuan Jing, T. Vladimirova

引用次数: 12

ABLUR: An FPGA-based adaptive deblurring core for real-time applications ABLUR:用于实时应用的基于fpga的自适应去模糊核心

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880165

Giuseppe Airò Farulla, Marco Indaco, P. Prinetto, Daniele Rolfo, Pascal Trotta

引用次数: 1

On enhancing the reliability of internal configuration controllers in FPGAs 提高fpga内部组态控制器可靠性的研究

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880162

Ali Ebrahim, T. Arslan, X. Iturbe

引用次数: 16

Dynamic parallel reconfiguration for self-adaptive hardware architectures 自适应硬件架构的动态并行重构

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880180

Laurent Fiack, Benoît Miramond, A. Upegui, F. Vannel

{"title":"Dynamic parallel reconfiguration for self-adaptive hardware architectures","authors":"Laurent Fiack, Benoît Miramond, A. Upegui, F. Vannel","doi":"10.1109/AHS.2014.6880180","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880180","url":null,"abstract":"Adaptive Hardware Systems can rely on software or hardware adaptation. Software adaptation can be globally assimilated to mode switching, either at a technological or hardware level (DVFS, Idle processor mode ...), or at the application level (bandwidth adaptation in telecommunication, multispectral cameras, ...). Hardware adaptation corresponds to a deeper change in the internal organization of the computing architecture of an embedded system. It enables more powerful adaptation but is currently limited by the reconfiguration (tool and architecture) of today's FPGA devices. We present in this paper a multi-FPGA platform designed to exhibit unique computing capabilities. The joint design of the electronic board and the internal architecture of each reconfigurable device permits dynamic parallel (and not partial) reconfiguration of several parts of the system while maintaining global routing and local computation in the rest of the system. Dynamic parallel reconfiguration and technological independence are enabled by considering reconfiguration at coarse grain. We describe in the paper the hardware elements composing the platform. The specific design of the global system allowed us to reach a fully operational platform. We present statistical experiments to evaluate the inter-chip network capacity which show that our platform supports up to 18 parallel reconfigurations per second.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116253085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A novel Dynamic Partial Reconfiguration design for automatic white balance 一种新的自动白平衡动态部分重构设计

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS) Pub Date : 2014-07-14 DOI: 10.1109/AHS.2014.6880152

Jalal Khalifat, T. Arslan

{"title":"A novel Dynamic Partial Reconfiguration design for automatic white balance","authors":"Jalal Khalifat, T. Arslan","doi":"10.1109/AHS.2014.6880152","DOIUrl":"https://doi.org/10.1109/AHS.2014.6880152","url":null,"abstract":"Auto white balancing is the process of keeping the color of objects constant automatically under different illumination conditions by calculating a number of parameters from the image data. These parameters are used to change the image pixel values to keep the color constant. This paper discusses the Lam's auto white balance algorithm and presents a novel, high-performance and cost-effective implementation of the algorithm in Field Programmable Gate Arrays (FPGAs) using Dynamic Partial Reconfiguration (DPR) feature to exploit the FPGA resources over time and space. The paper shows that the system with DPR saves 25% of the resources compared to the static design. Moreover, the power consumption is reduced by 13%. On the other hand, the performance of the DPR design is compared to the static design through two different techniques. The first technique targets low resources utilisation and the second targets higher throughput rate while the resource utilisation is in the range of the static design. The results show that the performance of the second technique is better than the static design. The architectures are designed to process images of size 1920x1080 within 16.78ms, 15.06ms and 11ms for first DPR technique, static design and second DPR technique respectively. Our proposed hardware architecture is shown to outperform previous hardware implementations of the algorithm and is being capable of processing up to 550 MPixels/s.","PeriodicalId":428581,"journal":{"name":"2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115137848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1