A hierarchical fault tolerant system on the PAnDA device with low disruption

Abstract

This paper presents the concept of hierarchical reconfiguration strategies that can be applied to a circuit on a reconfigurable architecture to change the implementation without changing the functionality, and their use to overcome faults in a source agnostic way. The Programmable Analogue and Digital Array (PAnDA) is a novel FPGA-like reconfigurable architecture, with configuration options below the digital layer. The PAnDA architecture includes symmetry and homogeneity at multiple levels of the configuration hierarchy. These properties could be exploited to take advantage of redundant resources in the event of a fault. To demonstrate this, faults are injected, repeatedly and at random, to a configured logic function until functionality breaks. Reconfiguration strategies are then applied at random in repeated steps to the faulty circuit until functionality is restored (or a set number of steps have been taken). An experiment is conducted to investigate whether controlling the probability of picking a particular strategy at each step can improve the average efficiency of fault recovery for a given function. It is found that the average number of steps required to fix a fault can be reduced while it is possible to increase the average number of circuits that can be fixed.