{"title":"Precise exceptions in asynchronous processors","authors":"R. Manohar, M. Nyström, Alain J. Martin","doi":"10.1109/ARVLSI.2001.915547","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915547","url":null,"abstract":"The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous processors that does not block the instruction fetch when exceptions do not occur; the cost of the exception handling mechanism is only encountered when an exception occurs during execution - an infrequent event.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132115102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Programmable and adaptive analog filters using arrays of floating-gate circuits","authors":"M. Kucic, P. Hasler, J. Dugger, David V. Anderson","doi":"10.1109/ARVLSI.2001.915557","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915557","url":null,"abstract":"In this paper we describe a programmable and adaptive filter based on floating-gate technology We review the basics of floating-gate techniques and how they enable programmable and adaptive filter circuits. We describe our programmable filter concepts, and show experimental results of programmable filter operation. We also describe programming methods, and extend the programmability to a wide range of functions and circuits using the same approach. Further, we describe our techniques and custom programmer board for floating-gate programming of an IC. We show how to extend our programmable filters as adaptive filters both through weight perturbation methods and continuously adapting correlation rule methods.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117067029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-power asynchronous VLSI FIR filter","authors":"V. A. Bartlett, E. Grass","doi":"10.1109/ARVLSI.2001.915548","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915548","url":null,"abstract":"An asynchronous FIR filter, based on a single bit-plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coefficient-set. The proposed architecture has the property that coefficients in a sign-magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic receiver biasing for inter-chip communication","authors":"C. Gauthier, J. Sivagnaname, R.B. Brown","doi":"10.1109/ARVLSI.2001.915554","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915554","url":null,"abstract":"A noise cancellation circuit was designed to improve the performance of a single-ended source-synchronous I/O interface. Common-mode variations between the high-frequency data bits and the DC reference against which they are compared were nulled using negative feedback. The clock and its complement were filtered at the receiving chip to establish an average value, which corresponds to duty cycle. That value was amplified and fed back to correct the biasing of the I/O receivers in such a way that the clocks were received with 50% duty-cycle. The biasing is shared among all I/O receivers. A prototype was designed in the HP-14B CMOS process and demonstrated using a current-mode I/O receiver that was developed simultaneously. The power supply voltage was 2.5-V. Measured results indicated that the noise cancellation circuit improved the receiver's bandwidth improved by 12% (1020-Mb/s vs 910-Mb/s), and system's static power-supply rejection (between transmitter and receiver) improved by a factor of 3.75 (/spl Delta/V/sub DD/=750-mV vs/spl Delta/V/sub DD/=200-mV). A more I/O conventional interface was also implemented using this technique in a 0.18 /spl mu/m CMOS process. The simulation environment allowed for a direct comparison between a conventional voltage reference transmission scheme and the dynamic biasing technique given a mismatch in transmitter and receiver process corners, a 100 cm signal trace, and a 5% static power supply gradient between the two chips. Simulated results indicated that the use of dynamic biasing reduced the timing jitter in the received eye from 1.8 ns to 1.18 ns, for a 3.0 ns bit-time.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134164283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Logic design considerations for 0.5-volt CMOS","authors":"K. Hass, J. Venbrux, P. Bhatia","doi":"10.1109/ARVLSI.2001.915552","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915552","url":null,"abstract":"As the operation supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are lowered can render some conventional logic circuit systems unusable. Furthermore, some low voltage circuits are not robust when faced with normal variations in threshold voltage. This paper examines the design consideration for logic and memory circuits in very low voltage CMOS and compares simulated behavior with measurements of fabrication test circuits. These circuit examples were closed because they illustrate the unique design challenges of low voltage CMOS.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133752375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Width-adaptive data word architectures","authors":"R. Manohar","doi":"10.1109/ARVLSI.2001.915555","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915555","url":null,"abstract":"We discuss number representations for width-adaptive data word architectures. The number representations are self-delimiting, permitting asynchronous implementations with dynamic width adaptivity and reduced energy-complexity. We describe how these architectures can be realized with asynchronous VLSI techniques, and show that they exhibit better energy and throughput characteristics than traditional asynchronous implementations. We study some of the tradeoffs in the design of this class of architectures.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"54 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126285052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chan-Ho Park, Byun-Soo Choi, Dong-Ik Lee, Ho-Yong Choi
{"title":"Asynchronous array multiplier with an asymmetric parallel array structure","authors":"Chan-Ho Park, Byun-Soo Choi, Dong-Ik Lee, Ho-Yong Choi","doi":"10.1109/ARVLSI.2001.915561","DOIUrl":"https://doi.org/10.1109/ARVLSI.2001.915561","url":null,"abstract":"In this paper an asynchronous array multiplier with a new parallel structure is introduced. This parallel array structure is designed to make the computation time faster with lower power consumption. An asymmetric array structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional Booth encoding array structures and that the multiplier with the proposed array structure shows reduction of 40% in the computational time with relatively lower power consumption.","PeriodicalId":424368,"journal":{"name":"Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126119365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}