Dynamic receiver biasing for inter-chip communication

A noise cancellation circuit was designed to improve the performance of a single-ended source-synchronous I/O interface. Common-mode variations between the high-frequency data bits and the DC reference against which they are compared were nulled using negative feedback. The clock and its complement were filtered at the receiving chip to establish an average value, which corresponds to duty cycle. That value was amplified and fed back to correct the biasing of the I/O receivers in such a way that the clocks were received with 50% duty-cycle. The biasing is shared among all I/O receivers. A prototype was designed in the HP-14B CMOS process and demonstrated using a current-mode I/O receiver that was developed simultaneously. The power supply voltage was 2.5-V. Measured results indicated that the noise cancellation circuit improved the receiver's bandwidth improved by 12% (1020-Mb/s vs 910-Mb/s), and system's static power-supply rejection (between transmitter and receiver) improved by a factor of 3.75 (/spl Delta/V/sub DD/=750-mV vs/spl Delta/V/sub DD/=200-mV). A more I/O conventional interface was also implemented using this technique in a 0.18 /spl mu/m CMOS process. The simulation environment allowed for a direct comparison between a conventional voltage reference transmission scheme and the dynamic biasing technique given a mismatch in transmitter and receiver process corners, a 100 cm signal trace, and a 5% static power supply gradient between the two chips. Simulated results indicated that the use of dynamic biasing reduced the timing jitter in the received eye from 1.8 ns to 1.18 ns, for a 3.0 ns bit-time.