2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization 面向视频摘要的基于交叉栏的内存处理架构

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00091

Nagadastagiri Challapalle, Makesh Chandran, Sahithi Rampalli, N. Vijaykrishnan

{"title":"X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization","authors":"Nagadastagiri Challapalle, Makesh Chandran, Sahithi Rampalli, N. Vijaykrishnan","doi":"10.1109/ISVLSI49217.2020.00091","DOIUrl":"https://doi.org/10.1109/ISVLSI49217.2020.00091","url":null,"abstract":"Video summarization techniques identify the most interesting frames in a video based on their uniqueness/importance or relevance to a user query. Deep learning based automated video summarization techniques have gained significant importance due to the growing need to analyze the exploding video data from user devices, surveillance cameras, and social media platforms etc. In contrast to the image classification, object detection tasks which predominantly use convolutional neural networks (CNNs), video summarization techniques comprise a pipeline of more diverse networks such as text processing networks, attention and content similarity mechanisms. In this work, we present X-VS, a ReRAM processing-in-memory (PIM) hardware accelerator architecture for video summarization workloads. We augment a baseline ReRAM CNN accelerator with a systolic array-based crossbar architecture to incorporate efficient support for recurrent neural networks, attention and content similarity mechanisms and hash-based word embedding lookup to support the video summarization networks. The proposed architecture achieves an average speedup of '450x, and energy savings of '1600x for two state-of-the-art video summarization networks over CPU and GPU implementations.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115448731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Fast Transient Digitally Assisted Flash-Based Modular LDO for Sensor Nodes in WBAN WBAN传感器节点快速瞬态数字辅助flash模块化LDO

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00073

Jitumani Sarma, Shatadal Chatterjee, Rakesh Biswas, Sounak Roy

引用次数: 2

ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs 用于纯函数式程序的并行加速器体系结构

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00070

Ricardo Coelho, Felipe Tanus, Álvaro Freitas Moreira, G. Nazar

{"title":"ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs","authors":"Ricardo Coelho, Felipe Tanus, Álvaro Freitas Moreira, G. Nazar","doi":"10.1109/isvlsi49217.2020.00070","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00070","url":null,"abstract":"Typical reconfigurable accelerators are either limited to instruction-level parallelism or require developers to manage parallelism in the source code manually. Pure functional languages simplify this task because they disallow the occurrence of side effects allowing safe and automatic identification of parallel operations. On the other hand, the higher level of abstraction of functional languages, when compared to imperative languages, typically makes the execution of functional programs less efficient. To improve this efficiency, we present ACQuA, a parallel accelerator that can be programmed with pure functional languages. ACQuA exploits the parallelism available in independent function calls, using hardware support and a dedicated memory organization to minimize the overheads of scheduling, communication, and synchronization. ACQuA also includes optimizations targeting the efficient execution of map, an important higher-order function in functional languages. We evaluate the effectiveness of these optimizations and ACQuA's scalability in terms of area and performance, showing near-optimal speedup for applications with independent function calls while using manageable amounts of hardware resources.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators 总线宽度感知芯片外存储器访问最小化CNN加速器

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00051

S. Tewari, Anshul Kumar, K. Paul

{"title":"Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators","authors":"S. Tewari, Anshul Kumar, K. Paul","doi":"10.1109/ISVLSI49217.2020.00051","DOIUrl":"https://doi.org/10.1109/ISVLSI49217.2020.00051","url":null,"abstract":"Convolutional Neural Network (CNN) accelerators have gained popularity due to their ability to speed up the CNN based applications. However, the energy efficiency of these accelerators is limiting their ubiquitous usage in energy-constrained devices. A significant fraction of their energy consumption results from off-chip memory accesses. In order to get high throughput, these accelerators connect to off-chip memory by a wide data bus. However, accessing the data of size, not a multiple of the bus width, results in wastage of energy. We observed that off-chip memory accesses could be reduced significantly by partitioning the data that optimally utilizes bus width and increases the number of aligned accesses. In this work, we propose a bus width aware approach to determine the optimal partition of the convolution layers to reduce the off-chip memory accesses. Our tool evaluates the off-chip memory accesses for different data partitions, and data reuse schemes to find the optimal partition. We have experimented with two popular CNNs, VGG16 and AlexNet. Our approach reduces off-chip memory accesses of VGG16 by 16% and 29% and of AlexNet by 9% and 16% on 64 and 128 bits data bus, respectively, compared to the state of the art approach.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114477520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Lightweight Ciphers on a 65 nm ASIC A Comparative Study on Energy Consumption 65纳米ASIC上的轻量级密码器及其能耗比较研究

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.000-2

Bastian Richter, A. Moradi

引用次数: 0

Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing 基于近似绝热逻辑的边缘计算低功耗高能效全加法器

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00064

Wu Yang, H. Thapliyal

{"title":"Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing","authors":"Wu Yang, H. Thapliyal","doi":"10.1109/isvlsi49217.2020.00064","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00064","url":null,"abstract":"The growing demands of data-intensive applications running on IoT edge devices require low-power and energyefficient circuits. Adiabatic logic recycles the energy and can develop energy-efficient circuits. Further, error-tolerant applications use approximate computing to reduce power consumption and area. Therefore, to investigate the benefits of approximate computing combined with adiabatic logic, we propose two adiabatic logic based approximate adders. The proposed approximate adders use the advantage of dual-rail logic to shrink the overall size and reduce energy consumption. The two proposed designs are True Sum Approximate Adder (TSAA) and True Carry-out Approximate Adder (TCAA). TSAA is approximating the Carryout based on the accurate Sum, and TCAA is approximating the Sum based on the accurate Carryout. We performed simulations using 45nm technology in Cadence Spectre. Comparing with CMOS based accurate mirror adder (AMA) at 100 MHz, a power-saving of 83.26% and energy saving of 66.54% in PFAL based TSAA (PFAL: Positive Feedback Adiabatic Logic) is achieved. Further, we achieved a power saving of 87.22% and an energy saving of 74.43% in PFAL based TCAA compared to CMOS based accurate mirror adder (AMA). It is illustrated that PFAL based TCAA consumes 24.0% less power and energy per cycle compared to PFAL based TSAA.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"68 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125960189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Practical Error Modeling Toward Realistic NISQ Simulation 面向现实NISQ仿真的实际误差建模

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00060

Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Y. Tabuchi, M. Hirokawa, Koji Inoue

引用次数: 0

Capacity Building Among European Stakeholders In the Areas of Cyber-Physical Systems, IoT & Embedded Systems: The SMART4ALL Digital Innovation Hub Perspective 欧洲利益相关者在网络物理系统、物联网和嵌入式系统领域的能力建设:SMART4ALL数字创新中心视角

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00-13

Christos P. Antonopoulos, G. Keramidas, V. Tsakanikas, Evi Faliagka, C. Panagiotou, N. Voros

{"title":"Capacity Building Among European Stakeholders In the Areas of Cyber-Physical Systems, IoT & Embedded Systems: The SMART4ALL Digital Innovation Hub Perspective","authors":"Christos P. Antonopoulos, G. Keramidas, V. Tsakanikas, Evi Faliagka, C. Panagiotou, N. Voros","doi":"10.1109/isvlsi49217.2020.00-13","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00-13","url":null,"abstract":"The goal of the SMART4ALL EU funded project is to build capacity amongst European stakeholders via the development of selfsustained, cross-border experiments that transfer knowledge and technology between academia and industry. It targets Customized Low Energy Computing (CLEC) in the Cyber-Physical (CPS) and the Internet of Things (IoT) domains by combining a set of unique characteristics that join together different cultures, different policies, different geographical areas, and different application domains. The SMART4ALL vision will be realized mainly through funded (via open calls) Pathfinder Application Experiments (PAEs) that will enable the transformation of academic knowledge into industry especially targeting South and Eastern European countries that are currently underrepresented in European funding opportunities. In this way community building, strategy development, and ecosystem learning are envisioned for boosting high-quality research and development in South Eastern Europe (SEE), through an efficient combination of regional, national and European policies. Furthermore SMART4ALL sets forward the concept of marketplace which is offered as a service (Marketplace-as-a-Service or MaaS) that acts as one-stop-smart-stop by offering tools, services, platforms based mainly on open sources technologies as well as technology suppliers - adopter matchmaking capabilities customized to the targeted thematic pillars of the project.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132867374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator 一种紧凑、高效、自适应、PVT不变的CMOS弛豫振荡器

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00011

Mounika Kelam, Balaji Yadav Battu, Zia Abbas

{"title":"A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator","authors":"Mounika Kelam, Balaji Yadav Battu, Zia Abbas","doi":"10.1109/ISVLSI49217.2020.00011","DOIUrl":"https://doi.org/10.1109/ISVLSI49217.2020.00011","url":null,"abstract":"This brief presents a novel PVT-invariant CMOS relaxation oscillator for Real-Time Clock (RTC) applications. The proposed design is compatible to work in a low supply voltage domain of SoC. The PVT invariance is achieved by a unique circuit implementation of introducing a self-adaptive mechanism that dynamically modifies the time constant of the oscillator core. Moreover, the design is accompanied by a digital calibration unit for further process compensation. Besides, the introduced supply independent bias circuit has greatly improved the supply regulation of the oscillator frequency. In addition, the design utilizes a complementary to absolute temperature (CTAT) current for temperature compensation. Area efficiency is enhanced by replacing bigger passive device i.e, resistor with an adaptive MOS resistor. The obtained results show that the minimum temperature coefficient (TC) of 31.236ppm/°C is achieved over a range of -40°C to 100°C. The resultant phase noise of -140dBc/Hz@1MHz is observed. The design has achieved a good power efficiency of 1.65nW/KHz at room temperature without a calibration unit. The line sensitivity (LS) of 0.1159%/V is noted in the range of 0.7V to 1.2V. Nevertheless, the entire system occupies an active area of 0.0509mm^2 with a power consumption of 90nW@0.7V. Also, the leakage current of the complete system is <54pA. Therefore, the proposed design aims at providing a production-friendly, ease of integration and low-cost solution.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK 基于ASAP7 PDK的工业路由器标准单元库的设计

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00080

Yuan-Dar Chung, Rung-Bin Lin

引用次数: 4