2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第2页

Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware Detectors 基于硬件的恶意软件检测中机器学习分类器的效率分析

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00-15

Abraham Peedikayil Kuruvila, Shamik Kundu, K. Basu

{"title":"Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware Detectors","authors":"Abraham Peedikayil Kuruvila, Shamik Kundu, K. Basu","doi":"10.1109/ISVLSI49217.2020.00-15","DOIUrl":"https://doi.org/10.1109/ISVLSI49217.2020.00-15","url":null,"abstract":"The emergence of promising Internet-of-things (IoT) empowered Consumer Electronic devices resulted in their exhaustive proliferation across several safety-critical architectures. As Malware continue to evolve and escalate in form factor and count in modern-day consumer electronics, identifying such malicious entities is highly imperative to avoid unanticipated system behaviour. Modern morphic Malware can hide itself under the garb of a benign program, thus, evading detection by a conventional anti-virus software. Hence, Malware detectors using Hardware Performance Counters (HPCs) are gaining traction in this domain. HPCs are a collective integration of special purpose registers utilised to track low-level micro-architectural events such as branches taken, cache hits, etc. Machine Learning classifiers are trained on the manifested HPC data and then deployed on Hardware-based Malware Detectors (HMDs), which efficiently detect the incognito Malware activity. This paper explores the performance of such traditional Machine Learning algorithms over the HPC values obtained at execution, to estimate the efficiency of classifying an application as Malware or benign. A thorough experimental analysis of the multivariate network parameters for each Machine Learning algorithm projects the Random Forest classifier to furnish a class-leading detection accuracy of 83.04%.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115588789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints R-Abax:一种满足TMR间距约束的辐射强化合法化算法

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00065

C. Georgakidis, C. Sotiriou, Nikolaos Sketopoulos, M. Krstic, O. Schrape, A. Breitenreiter

{"title":"R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints","authors":"C. Georgakidis, C. Sotiriou, Nikolaos Sketopoulos, M. Krstic, O. Schrape, A. Breitenreiter","doi":"10.1109/isvlsi49217.2020.00065","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00065","url":null,"abstract":"Faults caused by ionising radiation have become a significant reliability issue in modern ICs. However, the Radiation Hardening (RADHARD) design flow differs from the standard design flow. Thus, there is not sufficient support from industrial EDA tools. In this work, we present a Triple Modular Redundancy (TMR) Radiation Hardening (RADHARD) methodology, based on the replacement of Flip-Flops (FFs) to a TMR structure, consisting of a FF triplet and a majority voter, as well as a custom, Displacement-driven legalisation algorithm, called R-Abax, able to satisfy user-specified, minimum distances between the FFs of each triplet. Our RADHARD legalisation algorithm is fully compatible with existing EDA tools. By ensuring a minimum spacing between triplet FFs of each TMR structure, we reduce the probability of a particle strike affecting more than one triplet instances. We present the impact of our RADHARD flow, for a set of spacing constraints, to Power, Performance and Area (PPA) on a set of 11 OpenCores benchmarks. On average, a larger spacing between FF triplets worsens a design's Quality-of-Results (QoR), but not significantly, making our RADHARD flow attractive for reducing radiation faults.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115696665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Distributed Kriging-Bootstrapped DNN Model for Fast, Accurate Seizure Detection from EEG Signals 分布式kriging - bootstrap DNN模型用于快速、准确的脑电信号癫痫检测

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00055

Ibrahim L. Olokodana, S. Mohanty, E. Kougianos

{"title":"Distributed Kriging-Bootstrapped DNN Model for Fast, Accurate Seizure Detection from EEG Signals","authors":"Ibrahim L. Olokodana, S. Mohanty, E. Kougianos","doi":"10.1109/isvlsi49217.2020.00055","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00055","url":null,"abstract":"The modeling of the brain as a three-dimensional spatial object, similar to a geographical landscape, has the paved way for the successful application of Kriging methods in solving the seizure detection problem with good performance but in cubic computational time complexity. The Deep Neural Network (DNN) has been widely used for seizure detection due to its effectiveness in classification tasks, although at the cost of a protracted training time. While Kriging exploits the spatial correlation between data locations, DNN relies on its capacity to learn intrinsic representations within the dataset from the basest unit parts. This paper presents a Distributed Kriging-Bootstrapped Deep Neural Network (DNN) model as a twofold solution for fast and accurate seizure detection using brain signals collected with the electroencephalogram (EEG) from healthy subjects and patients of epilepsy. The proposed model parallelizes the Kriging computation into different cores in a machine and then produces a strongly correlated, unified quasi-output data which serves as an input to the Deep Neural Network. Experimental results validate the proposed model as superior to conventional Kriging methods and DNN by training in 91% less time than the basic DNN and about three times as fast as the ordinary Kriging-Bootstrapped Deep Neural Network (DNN) model while maintaining good performance in terms of sensitivity, specificity and testing accuracy compared to other models and existing works.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124541137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Area-Efficient Pipelined VLSI Architecture for Polar Decoder 面向极解码器的面积高效流水线VLSI架构

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00071

Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao

引用次数: 1

Classification and Workload Balancing of Multi-threaded Application on Embedded Platforms 嵌入式平台上多线程应用的分类与工作负载平衡

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00087

Rakesh Kumar, Bibhas Ghoshal

引用次数: 2

Design Automation for Field-Coupled Nanotechnologies 场耦合纳米技术的设计自动化

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00040

Marcel Walter, R. Drechsler

引用次数: 2

Advances in Molecular Quantum Computing: from Technological Modeling to Circuit Design 分子量子计算的进展:从技术建模到电路设计

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00033

G. Cirillo, G. Turvani, M. Simoni, M. Graziano

{"title":"Advances in Molecular Quantum Computing: from Technological Modeling to Circuit Design","authors":"G. Cirillo, G. Turvani, M. Simoni, M. Graziano","doi":"10.1109/isvlsi49217.2020.00033","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00033","url":null,"abstract":"Molecules are serious candidates for building hardware for quantum computers. They can encode quantum information onto electron or nuclear spins and some of them show important features as the scalability of the number of qubits and a universal set of quantum gates. In this paper we present our advances in the development of a classical simulation infrastructure for molecular Quantum Computing: starting from the definition of simplified models taking into account the main physical features of each analyzed molecule, quantum gates are defined over these models, thus permitting to take into account the real behavior of each technology during the simulation. An interface with a hardware-agnostic description language has been also developed. The knowledge of the behavior of real systems permits to optimize the design of quantum circuits at both physical and compilation levels. Elementary quantum algorithms have been simulated on three different molecular technologies by changing the physical parameters of polarization and manipulation and quantum circuit design strategies. Results confirm the dependency of the fidelity of the results on both levels, thus proving that the choice of optimal operating points and circuit optimization techniques as virtual-Z gates are fundamental for ensuring the execution of quantum circuits with negligible errors.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122077882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Secure-iGLU: A Secure Device for Noninvasive Glucose Measurement and Automatic Insulin Delivery in IoMT Framework Secure- iglu:一种在IoMT框架下无创血糖测量和自动胰岛素输送的安全装置

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00-17

A. Joshi, Prateek Jain, S. Mohanty

{"title":"Secure-iGLU: A Secure Device for Noninvasive Glucose Measurement and Automatic Insulin Delivery in IoMT Framework","authors":"A. Joshi, Prateek Jain, S. Mohanty","doi":"10.1109/ISVLSI49217.2020.00-17","DOIUrl":"https://doi.org/10.1109/ISVLSI49217.2020.00-17","url":null,"abstract":"The growth of healthcare technologies has made a great impact on human life for the last few years. Various innovations in implantable and wearable medical devices improve the quality of life. Internet-of-Medical-Things (IoMT) based smart healthcare with continuous sensing, connectivity, and automatic medication is the latest trend. With the growth of technologies and connectivity, the security of these devices is a growing concern. The security of medical devices is important as the security compromise may lead to critical situations. This paper explores the security aspect of the IoMT system with a non-invasive glucose monitoring device integrated with an insulin delivery system (called iGLU) as a specific example. We call this secure system as Secure-iGLU. The paper presents a Hardware-Assisted Security (HAS) paradigm using Physical Unclonable Function (PUF) to design Secure-iGLU. PUF is a useful primitive to generate fingerprint of the hardware, and it has a great potential to mitigate the security problem of iGLU. The simulation results confirm the security of our Secure-iGLU using PUF in IoMT with safe insulin delivery system.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122108230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization 基于systemc的虚拟原型的自动化设计理解:数据提取、分析和可视化

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/isvlsi49217.2020.00042

Mehran Goli, R. Drechsler

{"title":"Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization","authors":"Mehran Goli, R. Drechsler","doi":"10.1109/isvlsi49217.2020.00042","DOIUrl":"https://doi.org/10.1109/isvlsi49217.2020.00042","url":null,"abstract":"The ever-increasing functionality of modern electronic systems and reduced time-to-market constraints have significantly altered the typical design flow. One possible solution to deal with this rising complexity is to increase the level of abstraction toward the Electronic System Level (ESL). At the ESL, modeling system as a Virtual Prototype (VP) using SystemC and its Transaction Level Modeling (TLM) framework has become an industry-accepted solution in the last decade. VP design exploration, analysis, debugging, and integration of ever-changing functional requirements can be made faster, more accurate, and errorless with the help of a strong design understanding method. This paper presents a comprehensive automated design understanding methodology that enables designers to trace detailed information related to the VPs structure and behavior. The proposed methodology includes three main phases which are data extraction, analysis, and visualization. Experimental results including a real-world VP-based system show the advantages of our methodology such as its accuracy and applicability.","PeriodicalId":423851,"journal":{"name":"2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Retraining and Regularization to Optimize Neural Networks for Stochastic Computing 优化随机计算神经网络的再训练和正则化

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2020-07-01 DOI: 10.1109/ISVLSI49217.2020.00052

Junseok Oh, Florian Neugebauer, I. Polian, J. Hayes

引用次数: 0