2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)最新文献

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MRI brain tumor images classification using K-means clustering, NSCT and SVM 基于k -均值聚类、NSCT和SVM的MRI脑肿瘤图像分类
C. Saha, Md. Foisal Hossain
{"title":"MRI brain tumor images classification using K-means clustering, NSCT and SVM","authors":"C. Saha, Md. Foisal Hossain","doi":"10.1109/UPCON.2017.8251069","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251069","url":null,"abstract":"Magnetic Resonance Imaging (MRI) has justified its potential to be used as an emerging imaging tool for the anatomical examination of tissue in brain. Manual classification of a large number of MRI brain images of patients is anextremely time killing process and also susceptible to errors, so there is a need to develop a fast, accurate and automatic scheme for classifying MRI brain images. In this paper we present a scheme for the automatic classification of MRI brain images as normal, where tumor is not present or abnormal, where tumor is present using K-Means clustering, nonsubsampledcontourlet transform (NSCT) and support vector machine (SVM). In the preprocessing stage of this proposed scheme, median filter is used for removing noise and enhancing resolution of MRI brain images. Then K-means clustering is used for segmenting MRI brain imagesbecause it segments an image faster. Because of salient properties of NSCT like multiscale, multidirection and shift invariance, NSCT is applied to the segmented image. Then seven features are extracted from subband coefficients of NSCTand these features are applied to support vector machine for the classification of MRI brain images. The efficacy of this scheme is evaluated in terms of sensitivity, specificity and accuracy and this scheme exhibits classification accuracy rate 98.86% for GRB kernel SVM. This scheme is compared with other MRI brain images classification schemes and provides satisfactory results which clarify the effectiveness of our scheme.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116099266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Database normalization design pattern 数据库规范化设计模式
K. Kumar, S. K. Azad
{"title":"Database normalization design pattern","authors":"K. Kumar, S. K. Azad","doi":"10.1109/UPCON.2017.8251067","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251067","url":null,"abstract":"Normalization is a database design technique, which is used to design the Relational Database table up to higher normal form. The main aim of the database normalization approach is to reduce data redundancy and maintain the atomicity within the database table. In this paper, The Tabular approach algorithm method is introduced to generating candidate key from set a valid set of functional dependency. Once, it determines the candidate key of a database table from a given valid set of functional dependency, and then applying normalization algorithms we can easily achieve higher level of normal form. It also shows new tabular based automatic generation of all possible super key and candidate key of a database table. A tabular approach algorithm method have table, having three columns marked as left, middle and right and one row. This column contains the valid set of given functional dependency. Once, we feed the column of the tabular approach table marked as left, middle and right with all possible valid set of functional dependency, then using proposed tabular approach algorithm method used to determine candidate key(s) and using these key(s), we can reach higher level of normal form.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115243936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of a sixth-order higher bucking converter 六阶高抗压变换器的分析
Shrikant Misal, M. Veerachary
{"title":"Analysis of a sixth-order higher bucking converter","authors":"Shrikant Misal, M. Veerachary","doi":"10.1109/UPCON.2017.8251083","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251083","url":null,"abstract":"In this paper, a sixth-order buck converter facilitating higher bucking operation is proposed. This topology has a step-down gain which ideally varies between 0 and 1 for respective minimum and maximum duties of operation. The effectiveness of this topology is justified with respect to voltage gain, nature of source current and input filtering requirements. A steady-state analysis has been carried out for the converter and design equations for its circuit parameters are obtained. Also, the state-space model is formulated based on switching circuits and is utilized to design an effective voltage-mode controller. Steady-state and dynamic behaviour of this topology are verified using simulation and experimental studies.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122922335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure 基于新型锁存器结构的低功耗高速双尾动态CMOS比较器设计
R. Jain, Avaneesh K. Dubey, Vikrant Varshney, R. Nagaria
{"title":"Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure","authors":"R. Jain, Avaneesh K. Dubey, Vikrant Varshney, R. Nagaria","doi":"10.1109/UPCON.2017.8251050","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251050","url":null,"abstract":"Regenerative comparators due to its power efficiency and high-speed finds usage in many high-speed and low-power analog-to-digital converters. In this paper, a novel comparator based on double-tail architecture is proposed to enhance latch regeneration speed. Upon analyzing the delay expressions of some existing double-tail structures, the structure of latch stage is modified by adding cross-coupled transistors to improve latch regeneration thus enhancing comparison speed. Mathematical expression for total delay is also calculated for the proposed comparator. The proposed comparator is designed in CADENCE and simulated in SPECTRE at 90-nm CMOS technology. The simulation results indicate that for the proposed comparator energy per conversion and total delay are reduced by more than 40% and 20% respectively as compared to conventional double-tail dynamic comparator.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133457823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Tracking and erosion resistance of Liquid Silicone Rubber under normal and acidic environment 液体硅橡胶在正常和酸性环境下的跟踪和耐侵蚀性能
A. Verma, B. S. Reddy
{"title":"Tracking and erosion resistance of Liquid Silicone Rubber under normal and acidic environment","authors":"A. Verma, B. S. Reddy","doi":"10.1109/UPCON.2017.8251051","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251051","url":null,"abstract":"Performance evaluation is carried out for Liquid Silicone Rubber (LSR) insulators using tracking and erosion resistance. Present study is conducted for AC and positive DC stress for the normal contaminant as per IEC 60587 and acidic environment simulating acidic rain condition. An experimental arrangement is fabricated as per IEC 60587 and ASTM D-2303 standards and constant voltage method is employed to evaluate the tracking and erosion performance of LSR samples under normal and acidic environmental conditions. Physico-chemical analysis is performed on degraded samples using Scanning Electron Microscope (SEM), Energy dispersive X-ray (EDAX) Analysis and Fourier Transform Infra red Spectroscopy (FTIR). Comparative study is conducted for acid rain contaminant and standard contaminant of NH4Cl, further leakage current measurement is carried out for both AC and positive DC stress.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122178396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of SFS algorithm in control of DC motor and comparative analysis SFS算法在直流电机控制中的应用及对比分析
I. Khanam, G. Parmar
{"title":"Application of SFS algorithm in control of DC motor and comparative analysis","authors":"I. Khanam, G. Parmar","doi":"10.1109/UPCON.2017.8251057","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251057","url":null,"abstract":"The authors present an application of Stochastic Fractal Search (SFS) algorithm in control of DC motor. SFS algorithm uses the concept of Fractal. Here, integration of time multiplied absolute error (ITAE) has been taken as an objective function for tuning the parameters of PID controller by SFS algorithm. Comparison of proposed scheme (SFS/PID) with other existing techniques has also been shown. It has been observed that proposed SFS/PID approach with ITAE as an objective function gives no overshoot and other parameters such as; settling time and rise time are also comparable with other existing techniques. Also, the robustness analysis of proposed SFS/PID scheme has also been carried out with parameters' variation of DC motor along with the comparative analysis.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129560223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Modular multi-level converter topologies: Present status and key challenges 模块化多级转换器拓扑:现状和主要挑战
A. Yadav, S. Singh, S. Das
{"title":"Modular multi-level converter topologies: Present status and key challenges","authors":"A. Yadav, S. Singh, S. Das","doi":"10.1109/UPCON.2017.8251061","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251061","url":null,"abstract":"Modular multilevel converter (MMC) is an emerging technology for various applications including high voltage dc transmission and wind energy conversion systems. Submodule based MMC architecture dominates over other converters topologies, due to various technological as well as economic advantages. This paper presents a comprehensive review of MMC topology and its submodules. Different types of submodule architectures are discussed to provide an overview of evolving technology. Different submodules are grouped in accordance to their output terminal voltage levels. The key issues and challenges are also highlighted.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128461820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Keynote speaker: Computational Intelligence Technologies for Ambient Intelligence 主讲人:面向环境智能的计算智能技术
V. Piuri
{"title":"Keynote speaker: Computational Intelligence Technologies for Ambient Intelligence","authors":"V. Piuri","doi":"10.1109/UPCON.2017.8251141","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251141","url":null,"abstract":"Adaptability and advanced services for ambient intelligence require an intelligent technological support for understanding the current needs and the desires of users in the interactions with the environment for their daily use, as well as for understanding the current status of the environment also in complex situations. This infrastructure constitutes an essential base for smart living. Computational intelligence can provide additional flexible techniques for designing and implementing monitoring and control systems, which can be configured from behavioral examples or by mimicking approximate reasoning processes to achieve adaptable systems. This talk will analyze the opportunities offered by computational intelligence to support the realization of adaptable operations and intelligent services for smart living in an ambient intelligent infrastructure.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124639153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-objective optimization with non-convex cost functions using fuzzy mechanism based continuous genetic algorithm 基于模糊机制的连续遗传算法的非凸代价函数多目标优化
S. Parihar, Nitin Malik
{"title":"Multi-objective optimization with non-convex cost functions using fuzzy mechanism based continuous genetic algorithm","authors":"S. Parihar, Nitin Malik","doi":"10.1109/UPCON.2017.8251091","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251091","url":null,"abstract":"In this paper, a fuzzy mechanism based continuous genetic algorithm is employed to optimize the non-convex multi-objective problem for allocating power generation cost to all the generating units of the electrical system considering system constraints. Here, the total system cost for generation is optimized by considering Economic load dispatch and Environmental Dispatch simultaneously. The valve point loading effect is also considered in the proposed multi-objective problem to obtain Non-Convex Environmental Economic Dispatch problem. This biobjective problem is transformed as single objective problem considering price penalty factor. The proposed technique gives the best compromised solution with the highest rank out of the existing Pareto optimal solution set. The performance of the proposed method is confirmed and validated on two test systems having three and six generating units (IEEE-30 bus system). To show the dominance of the method the obtained results are further compared with the recently published result.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124009686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.45V, 1.3 nW bandgap CMOS voltage reference with temperature compensation 带温度补偿的0.45V, 1.3 nW带隙CMOS基准电压
Maxi Solanki, R. Khatri
{"title":"A 0.45V, 1.3 nW bandgap CMOS voltage reference with temperature compensation","authors":"Maxi Solanki, R. Khatri","doi":"10.1109/UPCON.2017.8251053","DOIUrl":"https://doi.org/10.1109/UPCON.2017.8251053","url":null,"abstract":"A sub-threshold CMOS band-gap voltage reference has been fabricated in SCL 180nm technology. With the progress of modern technology a fixed and constant DC supply voltage is needed for most of the circuit. The proposed circuit provides such reference voltage which is used in various ADCs and DACs. When the input voltage is in the range of 450mV to 1800mV, the output reference voltage is 197.8 mV which is the desirable output voltage for most of the analog circuits. The temperature coefficient is 85 ppm/°C for the range 0°C to 125°C, with an average current consumption of 3.15 nA. The PSRR for frequency less than 100 Hz is −39.4 dB and for frequency greater than 10 MHz is −7.6 dB. The obtained line sensitivity at an average is ≍0.786 %/V.","PeriodicalId":422673,"journal":{"name":"2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON)","volume":"48 51","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114058283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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