2013 5th International Conference on Computational Intelligence and Communication Networks最新文献_第4页

Active Noise Control Using Intrinsic Mode Function Technique 基于内禀模态函数技术的主动噪声控制

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.52

Neha Narang, M. Sharma, R. Vig

引用次数: 2

A Recurrent Neural Network Model for Lamprey-Like Robot Movement 类七鳃鳗机器人运动的递归神经网络模型

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.72

Bassam Daya, M. Chahine, R. Awad

引用次数: 1

Clustering of Preprocessed Web Usage Data Using ART1 Neural Network and Comparative Analysis of ART1, K-Means and SOM Clustering Techniques 基于ART1神经网络的预处理Web使用数据聚类及ART1、K-Means和SOM聚类技术的比较分析

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.73

H. Yogish, G. Raju

引用次数: 1

A Discrete-Time Sliding Mode Controller with Modified Function for Linear Time-Varying Systems 线性时变系统的带修正函数的离散滑模控制器

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.55

Shalabh Agarwal, Rajkumar, V. Deolia, V. Goyal

引用次数: 0

Fuzzy Based Routing Algorithm for Congestion Control in Internet 基于模糊路由的网络拥塞控制算法

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.67

N. Aggarwal, Deepak Gaur, Kunal Gupta

引用次数: 1

Cloud Server Optimization with Load Balancing and Green Computing Techniques Using Dynamic Compare and Balance Algorithm 使用动态比较和平衡算法的负载平衡和绿色计算技术的云服务器优化

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.114

Yatendra Sahu, R. K. Pateriya, R. Gupta

{"title":"Cloud Server Optimization with Load Balancing and Green Computing Techniques Using Dynamic Compare and Balance Algorithm","authors":"Yatendra Sahu, R. K. Pateriya, R. Gupta","doi":"10.1109/CICN.2013.114","DOIUrl":"https://doi.org/10.1109/CICN.2013.114","url":null,"abstract":"Cloud computing is a business oriented concept to provide online IT resources and IT services on demand using pay per use model where main goal of cloud service provider is to use cloud computing resources efficiently and gain profits marginally. One of the challenging areas in cloud computing is frequent optimization of cloud server. It mainly concerns with the load balancing of cloud data centers to improve efficiency of the host machine and minimize number of active host machine to support green computing concept. To balance the load of entire data center, we need to transfer the virtual machines of the overloaded host to the light weighted host using migration techniques. In this paper, we introduce a threshold based Dynamic compare and balance algorithm (DCABA) for cloud server optimization. Unlike the traditional server optimization strategies which consider only load balancing and scheduling of resources based on the usage of CPU, RAM and BW in physical servers, DCABA also minimizes the number of host machines to be powered on, for reducing the cost of cloud services. Our approach can serve the purpose of service cost reduction in cloud industry with effective utilization of available resources.","PeriodicalId":415274,"journal":{"name":"2013 5th International Conference on Computational Intelligence and Communication Networks","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114584351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 87

Unsupervised Speaker Segmentation and Clustering Using TESBCC and Pitch Based Features 基于TESBCC和音高特征的无监督说话人分割和聚类

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.142

J. Naresh, R. S. Holambe, T. Basu

引用次数: 1

A Comparative Study of Materialised View Selection in Data Warehouse Environment 数据仓库环境下物化视图选择的比较研究

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.100

Alka, A. Gosain

引用次数: 3

Simulation of Endpoint Based Call Admission Control Using Retransmission Timer 基于重传定时器的端点呼叫准入控制仿真

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.53

Amar Saraswat, Kunal Gupta

引用次数: 3

Power Reduction of ITC'99-b01 Benchmark Circuit Using Clock Gating Technique 利用时钟门控技术降低ITC'99-b01基准电路的功耗

2013 5th International Conference on Computational Intelligence and Communication Networks Pub Date : 2013-09-27 DOI: 10.1109/CICN.2013.93

Beer Pratap Singh Tomar, Vijayshri Chaurasia, J. Yadav, B. Pandey

{"title":"Power Reduction of ITC'99-b01 Benchmark Circuit Using Clock Gating Technique","authors":"Beer Pratap Singh Tomar, Vijayshri Chaurasia, J. Yadav, B. Pandey","doi":"10.1109/CICN.2013.93","DOIUrl":"https://doi.org/10.1109/CICN.2013.93","url":null,"abstract":"This paper, deals with Latch Free Clock Gating technique for reduction of clock power and dynamic power consumption in ITC'99 bo1 Benchmark circuit and we have compared power reduction at different device operating frequencies. Without latch free clock gating technique in b01 benchmark circuit the Contribution of Clock power was 37.50%, 37.64%, 4.46%, 38.75% and 38.76% of total dynamic power when device is operating at frequency 100MHz, 1GHz, 10GHz, 100GHz and 1 THz respectively. After implementation of latch free clock gating technique, In b01 benchmark circuit, Clock power contribution in total dynamic power reduces to 1.96%, 1.98%, 1.93% and 1.92%, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz respectively. We synthesized this device on 40-nm vertex-6 this technique also reduces significantly IOs power. We have shown last results only at two operating frequency i.e. 10GHz and 100GHz. At operating frequency of 1 THz, the proposed design results 97.08 % reduction in clock power, 7.28% reduction in IOs power and 44% reduction in dynamic power as compare d to ITC'99 b01 benchmark circuit without latch free clock gating technique.","PeriodicalId":415274,"journal":{"name":"2013 5th International Conference on Computational Intelligence and Communication Networks","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12