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[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools最新文献

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On the shortcomings of the axiomatic approach as presently used in computer science 论目前在计算机科学中使用的公理方法的缺点
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4951
R. Boute
{"title":"On the shortcomings of the axiomatic approach as presently used in computer science","authors":"R. Boute","doi":"10.1109/CMPEUR.1988.4951","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4951","url":null,"abstract":"In current practice, many issues in computer science are formulated and treated as formal logic theories, even though this style of axiomatization is inappropriate for the topic at hand. Comparison with the scientific approach in more mature disciplines, such as mathematics, physics and applied science, reveals the causes and the unwanted effects of this phenomenon and shows, more generally, that the methodological basis for computer science is still far from being fully developed. The impact on a few important research areas is briefly discussed. It is argued that this state of affairs can be improved by recognizing that the traditional characterization of the discipline of computer science, which may have been appropriate during the initial years, is now due for a major revision, and by broadening the 'pure' computer science curricula through the inclusion of judiciously chosen additional topics in mathematics, physics, and systems theory.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130981972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Formal specifications: an industrial case study 正式规范:一个工业案例研究
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4956
I. V. Horebeek, B. Vergauwen, J. Lewi
{"title":"Formal specifications: an industrial case study","authors":"I. V. Horebeek, B. Vergauwen, J. Lewi","doi":"10.1109/CMPEUR.1988.4956","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4956","url":null,"abstract":"The authors present an algebraic specification of two-party voice calls. Abstraction is made from technical details. Only relevant characteristics are specified. Emphasis is put on modularity and on a so-called object-oriented design methodology. As a vehicle for this exposition, the authors use a constructive algebraic specification language that allows rapid prototyping.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The automatic generation of graphical user interfaces 自动生成图形用户界面
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4965
R. Gabriel
{"title":"The automatic generation of graphical user interfaces","authors":"R. Gabriel","doi":"10.1109/CMPEUR.1988.4965","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4965","url":null,"abstract":"The author deals with the properties of a tool called G/sup 2/F (an editor generator for two-dimensional graphical formulas). G/sup 2/F makes it possible to define two-dimensional grammars graphically and to generate a corresponding syntax-directed editor. It facilitates syntactic-correctness-preserving operations on the abstract syntax trees of formulas and produces hardcopies of whole operation sequences on a laser printer. Thus, G/sup 2/F can be used to create user interfaces for a variety of applications. It is well suited to support a clear and surveyable representation of complex expressions which occur in every formal framework and to invoke procedures of an application transforming its abstract syntax.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Computer-aided design of self-testable VLSI circuits 自测试VLSI电路的计算机辅助设计
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4964
J. Kalinowski, A. Albicki
{"title":"Computer-aided design of self-testable VLSI circuits","authors":"J. Kalinowski, A. Albicki","doi":"10.1109/CMPEUR.1988.4964","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4964","url":null,"abstract":"The authors present the computer-aided self-test system, a CAD tool for designing of self-testable VLSI circuits. Given a register-transfer-level circuit graph and test requirements, CAST augments the circuit with features that make it self-testable. The objective of the CAST procedures is to maximize built-in test hardware in obtained designs. They give an example that illustrates the CAST design process. The CAST system can be easily extended to incorporate other high-level BIST (built-in self-test) techniques, such as the circular self-test path.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"75 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115076809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A technique for fault detection in C-testable orthogonal iterative arrays c可测试正交迭代阵列的故障检测技术
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4953
W. Huang, F. Lombardi
{"title":"A technique for fault detection in C-testable orthogonal iterative arrays","authors":"W. Huang, F. Lombardi","doi":"10.1109/CMPEUR.1988.4953","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4953","url":null,"abstract":"The authors present an approach to C-testability of orthogonal iterative arrays. C-testability is defined by those criteria which characterize the complexity of the testing process as independent of the dimensions of the array and of the erroneous states of the cells. The proposed approach is based on a cellular automata characterization under a single-faulty-cell assumption. This characterization analyzes the state transition table of a basic cell and adds new states to it. These new states are used to reproduce internally to the array the test input and propagate the faulty state to the output pins of a chip. This process is analyzed exhaustively. The characteristics of the additional states are presented. The conditions of C-testability are fully proved. Complexity of the testing process (number of test vectors) is discussed. It is proved that the proposed approach has a lower complexity than previously published work.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128168577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Guided synthesis and formal verification techniques for parameterized hardware modules 参数化硬件模块的指导性综合和形式化验证技术
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4938
L. Claesen, P. Johannes, D. Verkest, H. de Man
{"title":"Guided synthesis and formal verification techniques for parameterized hardware modules","authors":"L. Claesen, P. Johannes, D. Verkest, H. de Man","doi":"10.1109/CMPEUR.1988.4938","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4938","url":null,"abstract":"A method is proposed for either guided synthesis or formal correctness verification of parameterized digital hardware modules. It starts from a high-level parameterized description of the module, which is used as the specification. The method is based on the concept of correctness-preserving transformations. These transformations are described in a formal way by means of transformation descriptions. It ends at a lower-level parameterized structure description of the implementation. Direct manipulations are done using an existing hardware description language that emphasizes a strict separation between parameterized structure description and behavior description. The concepts have been applied to real VLSI design vehicles such as a pipelined and parameterized multiplier accumulator module and systolic implementation of an FIR filter. The methods presented here are easily adaptable to use in CAD.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115565339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A graph-based silicon compiler for concurrent VLSI systems 基于图形的并行VLSI系统编译器
[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools Pub Date : 1988-04-11 DOI: 10.1109/CMPEUR.1988.4932
R. Bergamaschi, D. Allerton
{"title":"A graph-based silicon compiler for concurrent VLSI systems","authors":"R. Bergamaschi, D. Allerton","doi":"10.1109/CMPEUR.1988.4932","DOIUrl":"https://doi.org/10.1109/CMPEUR.1988.4932","url":null,"abstract":"A silicon compiler able to synthesize concurrent VLSI systems is described. This compiler differs from most existing silicon compilers as there is no target architecture, and yet results have shown that it performs reasonably well for a range of applications. It features a novel technique for control-step partitioning based on a precedence graph. Concurrency is detected and extracted from the input description in order to generate a fast implementation. The graph, which corresponds to a state diagram of the circuit, is further optimized using a simple rule-based approach. A controller able to control any number of concurrent processes, based on a synchronous token-passing mechanism, is generated. Control signals are submitted to two-level and multilevel logic minimization, and they can be implemented either as a programmable logic arrays (PLA) or with standard cells. The data path is generated as a netlist of technology-independent parameterized cells which are mapped into cells from a library by a module binder. The final layout is automatically generated by placement-and-routing programs.<<ETX>>","PeriodicalId":415032,"journal":{"name":"[Proceedings] COMPEURO 88 - System Design: Concepts, Methods and Tools","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122887684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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