Asia and South Pacific Conference on Design Automation, 2006.最新文献_第9页

An anytime symmetry detection algorithm for ROBDDs 一种任意时刻的robdd对称检测算法

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118364

N. Kettle, A. King

引用次数: 8

Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system 对运行在硬实时系统上的任务进行功率感知调度和动态电压设置

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118416

Peng Rong, Massoud Pedram

引用次数: 65

Signal-path driven partition and placement for analog circuit 模拟电路的信号路径驱动分区和布局

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118462

Di Long, Xianlong Hong, Sheqin Dong

引用次数: 26

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems 数学辅助自适应体偏(ABB)温度补偿在千兆级大规模集成电路系统

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118433

Sanjay V. Kumar, C. Kim, S. Sapatnekar

引用次数: 29

Simultaneous block and I/O buffer floorplanning for flip-chip design 倒装芯片设计的同步块和I/O缓冲层规划

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118357

Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang

{"title":"Simultaneous block and I/O buffer floorplanning for flip-chip design","authors":"Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang","doi":"10.1145/1118299.1118357","DOIUrl":"https://doi.org/10.1145/1118299.1118357","url":null,"abstract":"The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Reducing dynamic compilation overhead by overlapping compilation and execution 通过重叠编译和执行减少动态编译开销

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118508

Priya Unnikrishnan, M. Kandemir, Feihui Li

{"title":"Reducing dynamic compilation overhead by overlapping compilation and execution","authors":"Priya Unnikrishnan, M. Kandemir, Feihui Li","doi":"10.1145/1118299.1118508","DOIUrl":"https://doi.org/10.1145/1118299.1118508","url":null,"abstract":"An important problem in executing applications in energy-sensitive embedded environments is to tune their behavior based on dynamic variations in energy constraints. One option for achieving this is dynamic compilation ~ compiling code fragments on the fly to adapt to changing energy demands. While dynamic compilation can be very beneficial in many embedded environments where multiple criteria need to be satisfied during execution, it can also incur a significant performance overhead since compilation takes place at runtime. The goal in this work is to reduce this performance overhead of dynamic compilation by overlapping it with application execution. Specifically, provided that we have available hardware resources to perform dynamic compilation concurrently with application execution, our approach compiles the next code fragment to be executed while we are executing the current code fragment. The experimental results from our implementation indicate significant savings in execution times. Our experimental results also indicate that the proposed strategy performs consistently well under different parameters","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"269-270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124011903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Robust analytical gate delay modeling for low voltage circuits 低压电路的鲁棒分析门延迟建模

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118315

Anand Ramalingam, S. Kodakara, A. Devgan, D. Pan

{"title":"Robust analytical gate delay modeling for low voltage circuits","authors":"Anand Ramalingam, S. Kodakara, A. Devgan, D. Pan","doi":"10.1145/1118299.1118315","DOIUrl":"https://doi.org/10.1145/1118299.1118315","url":null,"abstract":"Sakurai-Newton (SN) delay metric (Sakurai, 1990) is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that the SN metric fails to provide high accuracy and fidelity when CMOS gates operate at low supply voltages. Thus it may not be applicable in many low power applications with voltage scaling. In this paper, we propose a new closed form delay metric based on the centroid of power dissipation. This new metric is inspired by our key observation and theoretic proof that the SN delay is indeed Elmore delay, which can be viewed as the centroid of current. Our proposed metric has a very high correlation coefficient (ges 0.98) when correlated with the actual delays got from the HSPICE simulations. Such high correlation is consistent across all major process technologies. In comparison, the SN metric has a correlation coefficient between (0.70, 0.90) depending upon the technology and the CMOS gate, and it is less accurate for lower supply voltages. Since our proposed metric has high fidelity across a wide range of supply voltages yet a simple closed form, it is very useful to guide low voltage and low power designs","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130768703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits 组合电路和顺序电路中基于通过/失败的诊断测试向量的压缩

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118455

Y. Higami, K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Y. Takamatsu

引用次数: 19

Temperature-aware routing in 3D ICs 3D ic中的温度感知路由

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118377

Tianpei Zhang, Yong Zhan, S. Sapatnekar

引用次数: 106

Lazy BTB: reduce BTB energy consumption using dynamic profiling 惰性BTB:使用动态分析减少BTB能耗

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118506

Yen-Jen Chang

引用次数: 14