Asia and South Pacific Conference on Design Automation, 2006.最新文献

Utility of the OpenAccess database in academic research OpenAccess数据库在学术研究中的应用

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118408

D. Papa, I. Markov, P. Chong

引用次数: 1

Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications 数据主导应用中环路融合和环路移位的分层内存大小估计

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118442

Qubo Hu, Arnout Vandecappelle, M. Palkovic, P. G. Kjeldsberg, E. Brockmeyer, F. Catthoor

{"title":"Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications","authors":"Qubo Hu, Arnout Vandecappelle, M. Palkovic, P. G. Kjeldsberg, E. Brockmeyer, F. Catthoor","doi":"10.1145/1118299.1118442","DOIUrl":"https://doi.org/10.1145/1118299.1118442","url":null,"abstract":"Loop fusion and loop shifting are important transformations for improving data locality to reduce the number of costly accesses to off-chip memories. Since exploring the exact platform mapping for all the loop transformation alternatives is a time consuming process, heuristics steered by improved data locality are generally used. However, pure locality estimates do not sufficiently take into account the hierarchy of the memory platform. This paper presents a fast, incremental technique for hierarchical memory size requirement estimation for loop fusion and loop shifting at the early loop transformations design stage. As the exact memory platform is often not yet defined at this stage, we propose a platform-independent approach which reports the Pareto-optimal trade-off points for scratch-pad memory size and off-chip memory accesses. The estimation comes very close to the actual platform mapping. Experiments on realistic test-vehicles confirm that. It helps the designer or a tool to find the interesting loop transformations that should then be investigated in more depth afterward","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123049590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs 基于偏好有向图的混合信号soc快速基板噪声感知布局

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118476

Minsik Cho, Hongjoong Shin, D. Pan

{"title":"Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs","authors":"Minsik Cho, Hongjoong Shin, D. Pan","doi":"10.1145/1118299.1118476","DOIUrl":"https://doi.org/10.1145/1118299.1118476","url":null,"abstract":"In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of block preference directed graph (BPDG) and the classic sequence pair (SP) floorplan representation. Given a set of analog and digital blocks, the BPDG is constructed based on their inherent noise characteristics to capture their preferred relative orders for substrate noise minimization. For each sequence pair generated during floorplanning evaluation, we can measure its violation against BPDG very efficiently. We observe that by simply counting the number of violations obtained in this manner, it correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model has high fidelity to guide the substrate noise-aware floorplanning and layout optimization, which become a growing concern for mixed-signal/RF system on chips (SOC). Our experimental results show that the proposed approach is over 60/spl times/ faster than conventional floorplanning with even very compact substrate noise models. We also obtain less area and total substrate noise than the conventional approach.","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127381149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

OpenAccess overview: industrial experience OpenAccess概述:行业经验

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118406

Yoshio Inoue

引用次数: 2

Closed form solution for optimal buffer sizing using the Weierstrass elliptic function 使用weerstrass椭圆函数的最佳缓冲区大小的封闭形式解决方案

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118378

Sebastian Vogel, Martin D. F. Wong

引用次数: 0

A fast logic simulator using a look up table cascade emulator 使用查找表级联模拟器的快速逻辑模拟器

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118414

Hiroki Nakahara, Tsutomu Sasao, M. Matsuura

引用次数: 4

Crosstalk analysis using reconvergence correlation 利用再收敛相关进行串扰分析

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118318

Sachin Shrivastava, R. Pratap, H. Parameswaran, M. Verma

{"title":"Crosstalk analysis using reconvergence correlation","authors":"Sachin Shrivastava, R. Pratap, H. Parameswaran, M. Verma","doi":"10.1145/1118299.1118318","DOIUrl":"https://doi.org/10.1145/1118299.1118318","url":null,"abstract":"In the UDSM era, crosstalk is an area of considerable concern for designers, as it can have a considerable impact on the yield, both in terms of functionality and operating frequency. Methods of crosstalk analysis are pessimistic in nature and the effort is ongoing to come up with techniques that make the analysis as realistic as possible. Using information from timing analysis is one such technique where we use data about overlap in switching among nets to identify those that can potentially switch together. Existing techniques tend to look at the set of a victim and associated aggressor nets in isolation, and select a subset of aggressors based on the absolute timing windows of these nets, thus ignoring the information associated with the fanin of these nets. In reality, however, some of these nets may never switch together because the reconvergence of those nets has not being factored in. Ignoring this correlation can cause false failures being flagged, leading to increased design cycles and conservatism in the design. We propose a technique where the correlation due to reconvergence can be captured in terms of relative switching windows. We apply this technique to real designs and show that this leads to more realistic analysis for crosstalk, and that we can see a reduction in the number of violations reported. We also analyze the effective of the method statistically","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129511705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Using speculative computation and parallelizing techniques to improve scheduling of control based designs 利用推测计算和并行化技术改进基于控制设计的调度

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118502

R. Cordone, Fabrizio Ferrandi, M. Santambrogio, G. Palermo, D. Sciuto

引用次数: 8

An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model 一种基于仿射算法的自动、高效、静态位宽优化方法，实现最大位宽误差权衡

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118500

Y. Pu, Yajun Ha

引用次数: 26

Speed binning aware design methodology to improve profit under parameter variations 在参数变化情况下提高利润的速度感知设计方法

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118466

A. Datta, S. Bhunia, J. Choi, S. Mukhopadhyay, K. Roy

引用次数: 50