Asia and South Pacific Conference on Design Automation, 2006.最新文献_第8页

A fixed-die floorplanning algorithm using an analytical approach 一种基于解析方法的定模平面规划算法

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118477

Yong Zhan, Yan Feng, S. Sapatnekar

引用次数: 35

Fast multi-domain clock skew scheduling for peak current reduction 快速多域时钟倾斜调度的峰值电流降低

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118366

Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh

引用次数: 31

SAT-based optimal hypergraph partitioning with replication 基于sat的带复制的最优超图分区

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118480

M. Wrighton, A. DeHon

引用次数: 3

TAPHS: thermal-aware unified physical-level and high-level synthesis TAPHS:热感知统一的物理水平和高级合成

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118499

Zhenyu Gu, Yonghong Yang, Jia Wang, R. Dick, L. Shang

{"title":"TAPHS: thermal-aware unified physical-level and high-level synthesis","authors":"Zhenyu Gu, Yonghong Yang, Jia Wang, R. Dick, L. Shang","doi":"10.1145/1118299.1118499","DOIUrl":"https://doi.org/10.1145/1118299.1118499","url":null,"abstract":"Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performance. It is necessary to consider thermal effects during all levels of the design process, from the architectural level to the physical level. However, design-time temperature prediction requires access to block placement, wire models, power profile, and a chip-package thermal model. Thermal-aware design and synthesis necessarily couple architectural-level design decisions (e.g., scheduling) with physical design (e.g., floorplanning) and modeling (e.g., wire and thermal modeling). This article proposes an efficient and accurate thermal-aware floor-planning high-level synthesis system that makes use of integrated high-level and physical-level thermal optimization techniques. Voltage islands are automatically generated via novel slack distribution and voltage partitioning algorithms in order to reduce the design's power consumption and peak temperature. A new thermal-aware floorplanning technique is proposed to balance chip thermal profile, thereby further reducing peak temperature. The proposed system was used to synthesize a number of benchmarks, yielding numerous designs that trade off peak temperature, integrated circuit area, and power consumption. The proposed techniques reduces peak temperature by 12.5degC on average. When used to minimize peak temperature with a fixed area, peak temperature reductions are common. Under a constraint on peak temperature, integrated circuit area is reduced by 9.9% on average","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51

Parasitics extraction involving 3-D conductors based on multi-layered Green's function 基于多层格林函数的三维导体寄生物提取

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118461

Zuochang Ye, Zhiping Yu

引用次数: 3

Statistical Bellman-Ford algorithm with an application to retiming 统计Bellman-Ford算法及其在重定时中的应用

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118514

M. Ekpanyapong, Thaisiri Watewai, S. Lim

引用次数: 6

Object duplication for improving reliability 对象复制以提高可靠性

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118343

Guilin Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin

引用次数: 6

A routability constrained scan chain ordering technique for test power reduction 基于可达性约束的扫描链排序技术降低测试功耗

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118453

Xuan-Lun Huang, Jiun-Lang Huang

引用次数: 11

CGTA: current gain-based timing analysis for logic cells 基于电流增益的逻辑单元时序分析

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118316

Shahin Nazarian, Massoud Pedram, Tao Lin, E. Tuncer

引用次数: 0

Timing-driven placement based on monotone cell ordering constraints 基于单调单元排序约束的时序驱动布局

Asia and South Pacific Conference on Design Automation, 2006. Pub Date : 2006-01-24 DOI: 10.1145/1118299.1118355

Chanseok Hwang, Massoud Pedram

{"title":"Timing-driven placement based on monotone cell ordering constraints","authors":"Chanseok Hwang, Massoud Pedram","doi":"10.1145/1118299.1118355","DOIUrl":"https://doi.org/10.1145/1118299.1118355","url":null,"abstract":"In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.","PeriodicalId":413969,"journal":{"name":"Asia and South Pacific Conference on Design Automation, 2006.","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127377137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10