15th International Symposium on System Synthesis, 2002.最新文献

Efficient simulation of synthesis-oriented system level designs 面向综合的系统级设计的高效仿真

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581237

Rajesh K. Gupta, S. Shukla, N. Savoiu

{"title":"Efficient simulation of synthesis-oriented system level designs","authors":"Rajesh K. Gupta, S. Shukla, N. Savoiu","doi":"10.1145/581199.581237","DOIUrl":"https://doi.org/10.1145/581199.581237","url":null,"abstract":"Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware systems have some inherent parallelism efficiently expressing it depends on whether the target usage is synthesis or simulation. For synthesis, designs are usually described with synthesis tools in mind and are therefore partitioned according to the targeted hardware units. For simulation, runtime efficiency is critical but our previous work has shown that a synthesis-oriented description is not necessarily the most efficient, especially if using multiprocessor simulators. Multiprocessor simulation requires preemptive multithreading but most current C++-based high level system description languages use cooperative multithreading to exploit parallelism to reduce overhead. We have seen that, for synthesis-oriented models, along with adding preemptive threading we need to transform the threading structure for good simulation performance. In this paper we present an algorithm for automatically applying such transformations to C++-based hardware models, ongoing work aimed at proving the equivalence between the original and transformed model, and a 62% to 76% simulation time improvement on a dual processor simulator.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127473324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Optimal code size reduction for software-pipelined and unfolded loops 减少软件流水线和展开循环的最佳代码大小

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581232

Bin Xiao, Z. Shao, C. Phongpensri, E. Sha, Qingfeng Zhuge

引用次数: 5

System-level modeling of a network switch SoC 网络交换机SoC的系统级建模

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581215

A. Cassidy, Christopher P. Andrews, D. E. Thomas, J. M. Paul

引用次数: 3

Datapath merging and interconnection sharing for reconfigurable architectures 可重构体系结构的数据路径合并和互连共享

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581210

G. Araújo, S. Malik, Zhining Huang, N. Moreano

引用次数: 29

Security-driven exploration of cryptography in DSP cores 安全驱动的DSP核心密码学探索

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581218

C. Gebotys

引用次数: 2

Efficient power reduction techniques for time multiplexed address buses 时间复用地址总线的有效功率降低技术

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581246

N. Dutt, D. Hirschberg, M. Mamidipaka

{"title":"Efficient power reduction techniques for time multiplexed address buses","authors":"N. Dutt, D. Hirschberg, M. Mamidipaka","doi":"10.1145/581199.581246","DOIUrl":"https://doi.org/10.1145/581199.581246","url":null,"abstract":"We address the problem of reducing power dissipation on the time multiplexed address buses employed by contemporary DRAMs in SOC designs. We propose address encoding techniques to reduce the transition activity on the time-multiplexed address buses and hence reduce power dissipation. The reduction in transition activity is achieved by exploiting the principle of locality in address streams in addition to its sequential nature. We consider a realistic processor-memory architecture and apply the proposed techniques on the address streams derived from time-multiplexed DRAM addresses. Although the techniques by themselves axe not new, we show that a judicious combination of the existing techniques yield significant gains in power reductions. Experiments on SPEC95 benchmark programs show that our encoding techniques yield as much as 82% in transition activity compared to binary encoding. We show that these reductions amount to as much 60% reduction in the off-chip address bus power. Also since the encoder/decoder add some power overhead, we calculate the minimum off-chip bus capacitance to the internal node capacitance ratio needed to achieve power reductions.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"743 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

System-level abstraction semantics 系统级抽象语义

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581251

D. Gajski, A. Gerstlauer

引用次数: 60

Timing analysis of embedded software for speculative processors 投机处理器嵌入式软件的时序分析

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581229

Abhik Roychoudhury, Xianfeng Li, T. Mitra

引用次数: 20

System-level design of IEEE1394 bus segment bridge IEEE1394总线分段桥的系统级设计

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581217

T. Onoye, Yukihiro Nakamura, A. Shigiya, K. Chikamura, K. Tsujino, T. Izumi, H. Yamamoto

引用次数: 1

Design experience of a chip multiprocessor Merlot and expectation to functional verification 芯片多处理器梅洛的设计经验，并期望功能验证

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI: 10.1145/581199.581223

S. Matsushita

引用次数: 3